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* vc4: Try to pair up instructions when only one of them has PM bitBoyan Ding2015-09-171-47/+76
* vc4: convert from tgsi semantic/index to varying-slotEric Anholt2015-09-167-147/+106
* gallium/ttn: Convert to using VARYING_SLOT_* / FRAG_RESULT_*.Eric Anholt2015-09-163-10/+28
* vc4: Fix build from recent NIR cleanups.Eric Anholt2015-09-141-2/+1
* gallium: add PIPE_CAP_TGSI_TXQS to let st know if TXQS is supportedIlia Mirkin2015-09-131-0/+1
* vc4: Initialize pack field of qreg to 0 in qir_get_tempBoyan Ding2015-09-041-0/+1
* nir: Convert the builder to use the new NIR cursor API.Kenneth Graunke2015-08-272-4/+4
* gallium: add flags parameter to pipe_screen::context_createMarek Olšák2015-08-262-2/+2
* vc4: Actually allow math results to allocate into r4.Eric Anholt2015-08-212-1/+7
* vc4: Fold the 16-bit integer pack into the instructions generating it.Eric Anholt2015-08-215-30/+22
* vc4: Reuse QPU dumping for packing bits in QIR.Eric Anholt2015-08-213-22/+26
* vc4: Make _dest variants of qir ALU helpers to provide an explicit dest.Eric Anholt2015-08-212-4/+20
* vc4: Use the SSA defs list for figuring out eligible MOVs for copy prop.Eric Anholt2015-08-211-12/+10
* vc4: Add algebraic opt for rcp(1.0).Eric Anholt2015-08-201-0/+8
* vc4: Allow unpack_8[abcd]_f's src to stay in r4.Eric Anholt2015-08-201-1/+15
* vc4: Pack the unorm-packing bits into a src MUL instruction when possible.Eric Anholt2015-08-205-16/+104
* vc4: Add a QIR helper for whether the op is a MUL type.Eric Anholt2015-08-203-4/+16
* vc4: Drop an unused algebraic op.Eric Anholt2015-08-201-9/+0
* vc4: Switch QPU_PACK_SCALED to be two non-SSA instructions.Eric Anholt2015-08-205-21/+19
* vc4: Make the pack-to-unorm instructions be non-SSA.Eric Anholt2015-08-204-42/+36
* vc4: Allow QIR registers to be non-SSA.Eric Anholt2015-08-204-4/+10
* vc4: We can now move TEX_RESULT accesses across other r4 ops.Eric Anholt2015-08-201-16/+0
* util/ra: Make allocating conflict lists optionalJason Ekstrand2015-08-181-1/+1
* vc4: Move all of our fixed function fragment color handling to NIR.Eric Anholt2015-08-146-388/+538
* vc4: Add a helper for making driver-specific NIR load_uniform for GL stateEric Anholt2015-08-142-2/+30
* nir: Add a nir_opt_undef() to handle csels with undef.Eric Anholt2015-08-141-0/+1
* gallium: add an interface for EXT_depth_bounds_testMarek Olšák2015-08-141-0/+1
* gallium: add support for GLES texture float extensions (v3)Marek Olšák2015-08-141-0/+2
* vc4: add missing nir include, to fix the buildEmil Velikov2015-08-071-0/+1
* vc4: automake: remove unused includeEmil Velikov2015-08-071-1/+0
* vc4: Use nir_lower_load_const_to_scalar().Eric Anholt2015-08-041-0/+1
* vc4: Don't bother de-SSAing values that aren't part of phi webs.Eric Anholt2015-08-041-15/+44
* vc4: Don't bother saturating the dst color for blending.Eric Anholt2015-08-041-8/+2
* vc4: Make r4-writes implicitly move to a temp, and allocate temps to r4.Eric Anholt2015-08-048-107/+106
* vc4: Drop a dead prototype.Eric Anholt2015-08-041-8/+0
* vc4: Lower uniform loads to scalar in NIR.Eric Anholt2015-07-302-31/+81
* vc4: Move some FS input lowering into NIR.Eric Anholt2015-07-302-35/+50
* vc4: Move program keys to the header file.Eric Anholt2015-07-302-47/+49
* vc4: Lower NIR inputs to scalar as well.Eric Anholt2015-07-302-4/+44
* vc4: Start adding a NIR-based output lowering pass.Eric Anholt2015-07-304-7/+137
* vc4: Mark our shaders as single-threaded.Eric Anholt2015-07-302-0/+6
* vc4: Avoid leaking indirect array access UBOs.Eric Anholt2015-07-301-0/+2
* vc4: Avoid overflowing various static tables.Eric Anholt2015-07-304-4/+4
* vc4: Fix return values from recent validation changes.Eric Anholt2015-07-301-4/+4
* vc4: Skip re-emitting the shader_rec if it's unchanged.Eric Anholt2015-07-285-43/+158
* vc4: Drop unused vpm_offset value.Eric Anholt2015-07-281-3/+0
* vc4: Simplify vc4_use_bo and make sure it's not a shader.Eric Anholt2015-07-284-39/+26
* vc4: Keep the validated shader around for the simulator execution.Eric Anholt2015-07-283-13/+17
* vc4: Make the object be the return value from vc4_use_bo().Eric Anholt2015-07-283-23/+25
* vc4: Ensure that the bin CL is properly capped by increment/flush.Eric Anholt2015-07-283-26/+36
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