| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | vc4: Allow TLB Z/color/stencil writes from any ALU operation in QIR. | Eric Anholt | 2016-04-08 | 1 | -11/+24 |
| * | vc4: Add missing scheduling dependency for MS color writes. | Eric Anholt | 2016-04-08 | 1 | -0/+1 |
| * | vc4: Move discard handling to the condition flag. | Eric Anholt | 2016-03-16 | 1 | -5/+0 |
| * | vc4: Add missing braces in initializer | Rhys Kidd | 2016-02-15 | 1 | -1/+1 |
| * | vc4: Replace the SSA-style SEL operators with conditional MOVs. | Eric Anholt | 2016-01-06 | 1 | -4/+3 |
| * | vc4: Do instruction scheduling on the QIR to hide texture fetch latency. | Eric Anholt | 2015-12-18 | 1 | -0/+619 |
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