summaryrefslogtreecommitdiffstats
path: root/src/gallium/drivers/v3d
Commit message (Collapse)AuthorAgeFilesLines
* u_blitter: add a msaa parameter to util_blitter_clearPierre-Eric Pelloux-Prayer2019-07-231-1/+2
| | | | | | | Fixes: ea5b7de138b ("radeonsi: make gl_SampleMaskIn = 0x1 when MSAA is disabled") Tested-by: Michel Dänzer <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium: switch boolean -> bool at the interface definitionsIlia Mirkin2019-07-226-25/+25
| | | | | | | | | | | | | | | | | | This is a relatively minimal change to adjust all the gallium interfaces to use bool instead of boolean. I tried to avoid making unrelated changes inside of drivers to flip boolean -> bool to reduce the risk of regressions (the compiler will much more easily allow "dirty" values inside a char-based boolean than a C99 _Bool). This has been build-tested on amd64 with: Gallium drivers: nouveau r300 r600 radeonsi freedreno swrast etnaviv v3d vc4 i915 svga virgl swr panfrost iris lima kmsro Gallium st: mesa xa xvmc xvmc vdpau va Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Acked-by: Alyssa Rosenzweig <[email protected]>
* v3d: fill logicop_func in the fragment shader key when precompiling shadersIago Toral Quiroga2019-07-221-0/+2
| | | | | | | | | | | Since logicop_func 0 is PIPE_LOGIOP_CLEAR, we were trigger lowerinng of logic ops on precompiled shaders, which we don't want to do. Also, this had the side effect of making shader-db crash, as during this lowering we would try to read the color format swizzle information from the fragment shader key that we don't populate in precompiled shaders because right now we only need it when logic operations are enabled. Reviewed-by: Eric Anholt <[email protected]>
* broadcom: Move v3d_get_device_info to commonAndreas Bergmeier2019-07-171-51/+2
| | | | In common we can use implementation for Vulkan.
* v3d: flag dirty state when binding new sampler statesIago Toral Quiroga2019-07-161-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We emit code to saturate texture coordinates when using clamp wrapping mode so if we don't flag the dirty state here we don't get to recompile the shaders when the wrapping mode changes. v2: - Do the same when setting sampler views (Eric) - Use a switch statement instead of an if ladder. - Swap the shader stage assertion with an unreachable. Fixes: spec/!opengl 1.1/texwrap 1d bordercolor/gl_rgba8, border color only spec/!opengl 1.1/texwrap 1d proj bordercolor/gl_rgba8, projected, border color only spec/!opengl 1.1/texwrap 2d bordercolor/gl_rgba8, border color only spec/!opengl 1.1/texwrap 2d proj bordercolor/gl_rgba8, projected, border color only spec/!opengl 1.1/texwrap formats bordercolor-swizzled/gl_alpha12, swizzled, border color only spec/!opengl 1.1/texwrap formats bordercolor-swizzled/gl_alpha16, swizzled, border color only spec/!opengl 1.1/texwrap formats bordercolor-swizzled/gl_alpha4, swizzled, border color only spec/!opengl 1.1/texwrap formats bordercolor-swizzled/gl_alpha8, swizzled, border color only spec/!opengl 1.1/texwrap formats bordercolor-swizzled/gl_intensity8, swizzled, border color only spec/!opengl 1.1/texwrap formats bordercolor-swizzled/gl_luminance4_alpha4, swizzled, border color only spec/!opengl 1.1/texwrap formats bordercolor-swizzled/gl_luminance6_alpha2, swizzled, border color only spec/!opengl 1.1/texwrap formats bordercolor-swizzled/gl_luminance8, swizzled, border color only spec/!opengl 1.1/texwrap formats bordercolor-swizzled/gl_luminance8_alpha8, swizzled, border color only spec/!opengl 1.1/texwrap formats bordercolor-swizzled/gl_r3_g3_b2, swizzled, border color only spec/!opengl 1.1/texwrap formats bordercolor-swizzled/gl_rgb10, swizzled, border color only spec/!opengl 1.1/texwrap formats bordercolor-swizzled/gl_rgb10_a2, swizzled, border color only spec/!opengl 1.1/texwrap formats bordercolor-swizzled/gl_rgb4, swizzled, border color only spec/!opengl 1.1/texwrap formats bordercolor-swizzled/gl_rgb5, swizzled, border color only spec/!opengl 1.1/texwrap formats bordercolor-swizzled/gl_rgb5_a1, swizzled, border color only spec/!opengl 1.1/texwrap formats bordercolor-swizzled/gl_rgb8, swizzled, border color only spec/!opengl 1.1/texwrap formats bordercolor-swizzled/gl_rgba4, swizzled, border color only spec/!opengl 1.1/texwrap formats bordercolor-swizzled/gl_rgba8, swizzled, border color only spec/!opengl 1.1/texwrap formats bordercolor/gl_alpha12, border color only spec/!opengl 1.1/texwrap formats bordercolor/gl_alpha16, border color only spec/!opengl 1.1/texwrap formats bordercolor/gl_alpha4, border color only spec/!opengl 1.1/texwrap formats bordercolor/gl_alpha8, border color only spec/!opengl 1.1/texwrap formats bordercolor/gl_intensity8, border color only spec/!opengl 1.1/texwrap formats bordercolor/gl_luminance4_alpha4, border color only spec/!opengl 1.1/texwrap formats bordercolor/gl_luminance6_alpha2, border color only spec/!opengl 1.1/texwrap formats bordercolor/gl_luminance8, border color only spec/!opengl 1.1/texwrap formats bordercolor/gl_luminance8_alpha8, border color only spec/!opengl 1.1/texwrap formats bordercolor/gl_r3_g3_b2, border color only spec/!opengl 1.1/texwrap formats bordercolor/gl_rgb10, border color only spec/!opengl 1.1/texwrap formats bordercolor/gl_rgb10_a2, border color only spec/!opengl 1.1/texwrap formats bordercolor/gl_rgb4, border color only spec/!opengl 1.1/texwrap formats bordercolor/gl_rgb5, border color only spec/!opengl 1.1/texwrap formats bordercolor/gl_rgb5_a1, border color only spec/!opengl 1.1/texwrap formats bordercolor/gl_rgb8, border color only spec/!opengl 1.1/texwrap formats bordercolor/gl_rgba4, border color only spec/!opengl 1.1/texwrap formats bordercolor/gl_rgba8, border color only spec/!opengl 1.2/texwrap 3d bordercolor/gl_rgba8, border color only spec/!opengl 1.2/texwrap 3d proj bordercolor/gl_rgba8, projected, border color only spec/arb_es2_compatibility/texwrap formats bordercolor-swizzled/gl_rgb565, swizzled, border color only spec/arb_es2_compatibility/texwrap formats bordercolor/gl_rgb565, border color only spec/arb_texture_compression/texwrap formats bordercolor-swizzled/gl_compressed_alpha, swizzled, border color only spec/arb_texture_compression/texwrap formats bordercolor-swizzled/gl_compressed_luminance_alpha, swizzled, border color only spec/arb_texture_compression/texwrap formats bordercolor-swizzled/gl_compressed_rgb, swizzled, border color only spec/arb_texture_compression/texwrap formats bordercolor/gl_compressed_alpha, border color only spec/arb_texture_compression/texwrap formats bordercolor/gl_compressed_luminance_alpha, border color only spec/arb_texture_compression/texwrap formats bordercolor/gl_compressed_rgb, border color only spec/arb_texture_float/texwrap formats bordercolor-swizzled/gl_alpha16f_arb, swizzled, border color only spec/arb_texture_float/texwrap formats bordercolor-swizzled/gl_intensity16f_arb, swizzled, border color only spec/arb_texture_float/texwrap formats bordercolor-swizzled/gl_luminance16f_arb, swizzled, border color only spec/arb_texture_float/texwrap formats bordercolor-swizzled/gl_luminance_alpha16f_arb, swizzled, border color only spec/arb_texture_float/texwrap formats bordercolor-swizzled/gl_rgb16f, swizzled, border color only spec/arb_texture_float/texwrap formats bordercolor-swizzled/gl_rgba16f, swizzled, border color only spec/arb_texture_float/texwrap formats bordercolor/gl_alpha16f_arb, border color only spec/arb_texture_float/texwrap formats bordercolor/gl_intensity16f_arb, border color only spec/arb_texture_float/texwrap formats bordercolor/gl_luminance16f_arb, border color only spec/arb_texture_float/texwrap formats bordercolor/gl_luminance_alpha16f_arb, border color only spec/arb_texture_float/texwrap formats bordercolor/gl_rgb16f, border color only spec/arb_texture_float/texwrap formats bordercolor/gl_rgba16f, border color only spec/arb_texture_rectangle/texwrap rect bordercolor/gl_rgba8, border color only spec/arb_texture_rectangle/texwrap rect proj bordercolor/gl_rgba8, projected, border color only spec/arb_texture_rg/texwrap formats bordercolor-swizzled/gl_r8, swizzled, border color only spec/arb_texture_rg/texwrap formats bordercolor-swizzled/gl_rg8, swizzled, border color only spec/arb_texture_rg/texwrap formats bordercolor/gl_r8, border color only spec/arb_texture_rg/texwrap formats bordercolor/gl_rg8, border color only spec/arb_texture_rg/texwrap formats-float bordercolor-swizzled/gl_r16f, swizzled, border color only spec/arb_texture_rg/texwrap formats-float bordercolor-swizzled/gl_rg16f, swizzled, border color only spec/arb_texture_rg/texwrap formats-float bordercolor/gl_r16f, border color only spec/arb_texture_rg/texwrap formats-float bordercolor/gl_rg16f, border color only spec/ext_packed_float/texwrap formats bordercolor-swizzled/gl_r11f_g11f_b10f, swizzled, border color only spec/ext_packed_float/texwrap formats bordercolor/gl_r11f_g11f_b10f, border color only spec/ext_texture_shared_exponent/texwrap formats bordercolor-swizzled/gl_rgb9_e5, swizzled, border color only spec/ext_texture_shared_exponent/texwrap formats bordercolor/gl_rgb9_e5, border color only spec/ext_texture_snorm/texwrap formats bordercolor-swizzled/gl_alpha8_snorm, swizzled, border color only spec/ext_texture_snorm/texwrap formats bordercolor-swizzled/gl_intensity8_snorm, swizzled, border color only spec/ext_texture_snorm/texwrap formats bordercolor-swizzled/gl_luminance8_alpha8_snorm, swizzled, border color only spec/ext_texture_snorm/texwrap formats bordercolor-swizzled/gl_luminance8_snorm, swizzled, border color only spec/ext_texture_snorm/texwrap formats bordercolor-swizzled/gl_r8_snorm, swizzled, border color only spec/ext_texture_snorm/texwrap formats bordercolor-swizzled/gl_rg8_snorm, swizzled, border color only spec/ext_texture_snorm/texwrap formats bordercolor-swizzled/gl_rgb8_snorm, swizzled, border color only spec/ext_texture_snorm/texwrap formats bordercolor-swizzled/gl_rgba8_snorm, swizzled, border color only spec/ext_texture_snorm/texwrap formats bordercolor/gl_alpha8_snorm, border color only spec/ext_texture_snorm/texwrap formats bordercolor/gl_intensity8_snorm, border color only spec/ext_texture_snorm/texwrap formats bordercolor/gl_luminance8_alpha8_snorm, border color only spec/ext_texture_snorm/texwrap formats bordercolor/gl_luminance8_snorm, border color only spec/ext_texture_snorm/texwrap formats bordercolor/gl_r8_snorm, border color only spec/ext_texture_snorm/texwrap formats bordercolor/gl_rg8_snorm, border color only spec/ext_texture_snorm/texwrap formats bordercolor/gl_rgb8_snorm, border color only spec/ext_texture_snorm/texwrap formats bordercolor/gl_rgba8_snorm, border color only spec/ext_texture_srgb/texwrap formats bordercolor-swizzled/gl_sluminance8, swizzled, border color only spec/ext_texture_srgb/texwrap formats bordercolor-swizzled/gl_sluminance8_alpha8, swizzled, border color only spec/ext_texture_srgb/texwrap formats bordercolor-swizzled/gl_srgb8, swizzled, border color only spec/ext_texture_srgb/texwrap formats bordercolor-swizzled/gl_srgb8_alpha8, swizzled, border color only spec/ext_texture_srgb/texwrap formats bordercolor/gl_sluminance8, border color only spec/ext_texture_srgb/texwrap formats bordercolor/gl_sluminance8_alpha8, border color only spec/ext_texture_srgb/texwrap formats bordercolor/gl_srgb8, border color only spec/ext_texture_srgb/texwrap formats bordercolor/gl_srgb8_alpha8, border color only Reviewed-by: Eric Anholt <[email protected]>
* v3d: acquire scoreboard lock before first tlb readIago Toral Quiroga2019-07-121-0/+2
| | | | | | | | | | | | | | | | | | | Until now we have always been emitting our scoreboard locks on the last thread switch to improve parallelism. We did this by emitting our last thread switch right before our tlb writes at the very end of the program, where we know that we are outside control flow. Unfortunately, this strategy is not valid when we have tlb color reads too, as these will happen before this point in the program and can happen inside control flow. To fix this we always emit a thread switch before the first tlb load and if we see additional thread switches after that point, we change the strategy to lock on the first thread switch. v2: change the solution so it is expected to work in more scenarios (Eric). Reviewed-by: Eric Anholt <[email protected]>
* v3d: add color formats and swizzles to the fragment shader keyIago Toral Quiroga2019-07-121-0/+11
| | | | | | | We are going to need these very soon to emit correct reads from the tlb to implement logic operations. Reviewed-by: Eric Anholt <[email protected]>
* gallium: get rid of PIPE_CAP_SM3Erik Faye-Lund2019-07-101-1/+3
| | | | | | | | | | | | | | | | | | | | | PIPE_CAP_SM3 has always been an odd one out of all our caps. While most other caps are fine-grained and single-purpose, this cap encode several features in one. And since OpenGL cares more about single features, it'd be nice to get rid of this one. As it turns, this is now relatively simple. We only really care about three features using this cap, and those already got their own caps. So we can remove it, and make sure all current drivers just give the same response to all of them. The only place we *really* care about SM3 is in nine, and there we can instead just re-construct the information based on the finer-grained caps. This avoids DX9 semantics from needlessly leaking into all of the drivers, most of who doesn't care a whole lot about DX9 specifically. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Acked-by: Alyssa Rosenzweig <[email protected]>
* v3d: Early return with handle 0 when getting a bo on the simulatorAlejandro Piñeiro2019-07-091-0/+3
| | | | | | | | | | | | | Until now we were just asking entries on the bo hash table, and don't worry if the handle was NULL, as we were just expecting to get a NULL in return. It seems that now the hash table assert with some reserverd pointers, included NULL. This commit just early returns with handle 0. This change fixes several crashes on vk-gl-cts GLES tests when using the v3d simulator, like: KHR-GLES3.core.internalformat.copy_tex_image.* Reviewed-by: Eric Anholt <[email protected]>
* v3d: do not flush jobs that are synced with 'Wait for transform feedback'Iago Toral Quiroga2019-07-025-20/+61
| | | | | | | | | | | | | Generally, we achieve this by skipping the flush on calls to v3d_flush_jobs_writing_resource() when we detect that the resource is written in the current job from a transform feedback write. The exception to this is the case where the caller is about to map the resource, in which case we need to flush immediately since we can only emit 'Wait for transform feedback' commands on rendering jobs. We add a parameter to the function so the caller can identify that scenario. Reviewed-by: Eric Anholt <[email protected]>
* v3d: emit 'Wait for transform feedback' commands when neededIago Toral Quiroga2019-07-021-0/+120
| | | | | | | | | | | | | | | | | | | | | | The hardware can flush transform feedback writes before reads in the same job by inserting this command. This patch detects when the rendering state for the current draw call reads resources that had been previously written by transform feedback in the same job and inserts the 'Wait for transform feedback' command before emitting the new draw. v2 (Eric): - this was intended to look at job->tf_write_prscs for TF jobs. - clear job->tf_write_prscs after we emit the TF flush. - can skip flushes for fragment shader reads from TF. v3 (Eric): - all resources in job->tf_write_prscs are resources written by TF so we don't need to check if they are bound to PIPE_BIND_STREAM_OUTPUT. - documented optimization opportunity for geometry stages. Reviewed-by: Eric Anholt <[email protected]>
* v3d: keep track of resources written by transform feedbackIago Toral Quiroga2019-07-023-2/+15
| | | | | | | | | | | | | The hardware provides a feature to sync reads from previous transform feedback writes in the same job so if we use this mechanism we no longer have to flush the job. In order to identify this scenario we need a mechanism to identify resources that are written by transform feedback. v2: use _mesa_pointer_set_create (Eric) Reviewed-by: Eric Anholt <[email protected]>
* v3d: flush jobs writing to vertex buffers used in the current draw callIago Toral Quiroga2019-06-211-0/+9
| | | | | | | | | | | | | | | This can happen when any of our vertex buffers was written by a previous transform feedback draw. Fixes the following piglit tests: spec/ext_transform_feedback/position-render-bufferbase spec/ext_transform_feedback/position-render-bufferbase-discard spec/ext_transform_feedback/position-render-bufferoffset spec/ext_transform_feedback/position-render-bufferoffset-discard spec/ext_transform_feedback/position-render-bufferrange spec/ext_transform_feedback/position-render-bufferrange-discard Reviewed-by: Eric Anholt <[email protected]>
* v3d: flush jobs reading from transform feedback output buffersIago Toral Quiroga2019-06-211-2/+24
| | | | | | | | | | | If we are about to write to a transform feedback buffer, we should make sure that we flush any prior work that intended to read from any of these buffers. Fixes piglit test: spec/ext_transform_feedback/immediate-reuse Reviewed-by: Eric Anholt <[email protected]>
* v3d: add a helper to check if transform feedback is enabledIago Toral Quiroga2019-06-212-2/+8
| | | | | | v2: We should be safe assuming that bind_vs != NULL (Eric) Reviewed-by: Eric Anholt <[email protected]>
* v3d: only flush jobs accessing the query BO when reading query resultsIago Toral Quiroga2019-06-181-2/+2
| | | | Reviewed-by: Eric Anholt <[email protected]>
* v3d: add a helper function to flush jobs using a BOIago Toral Quiroga2019-06-182-0/+12
| | | | | | v2: use _mesa_set_search() (Eric) Reviewed-by: Eric Anholt <[email protected]>
* v3d: don't emit point coordinates varyings if the FS doesn't read themIago Toral Quiroga2019-06-071-0/+5
| | | | | | | We still need to emit them in V3D 3.x since there there is no mechanism to disable them. Reviewed-by: Eric Anholt <[email protected]>
* v3d: Use driconf to expose non-MSAA texture limits for Xorg.Eric Anholt2019-05-134-3/+38
| | | | | | The V3D 4.2 HW has a limit to MSAA texture sizes of 4096. With non-MSAA, we can go up to 7680 (actually probably 8138, but that hasn't been validated by the HW team). Exposing 7680 in X11 will allow dual 4k displays.
* gallium: Redefine the max texture 2d cap from _LEVELS to _SIZE.Eric Anholt2019-05-131-1/+5
| | | | | | | | The _LEVELS assumes that the max is always power of two. For V3D 4.2, we can support up to 7680 non-power-of-two MSAA textures, which will let X11 support dual 4k displays on newer hardware. Reviewed-by: Marek Olšák <[email protected]>
* Revert "v3d: Disable PIPE_CAP_BLIT_BASED_TEXTURE_TRANSFER."Eric Anholt2019-04-261-1/+9
| | | | | | This reverts commit ccce9409470c1053c40c822d759b9bd417062bc0, leaving a note as to why we had to (corruption in chromium, breaking some GLES3.1 tests).
* v3d: Don't try to update the shadow texture for separate stencil.Eric Anholt2019-04-261-1/+2
| | | | | | | | | | | There are two cases where v3d's sampler view's resource doesn't match the base's: shadow textures for sampling from raster, and pointing at the separate depth texture for z32f_s8x24. We only want to update shadow for the first case. Fixes dEQP-GLES31.functional.stencil_texturing.render.depth32f_stencil8_draw when run after the previous testcase.
* v3d: Use _mesa_hash_table_remove_key() where appropriate.Eric Anholt2019-04-261-13/+8
|
* v3d: Apply the GFXH-930 workaround to the case where the VS loads attrs.Eric Anholt2019-04-261-0/+15
| | | | | | | We were emitting a dummy load for when the VS doesn't load any attributes, but we also need to emit a dummy load for when the render VS loads attributes but the binner VS doesn't. Fixes simulator assertion failures and GPU hangs on KHR-GLES31.core.texture_gather.\*
* v3d: Fill in the ignored segment size fields to appease new simulator.Eric Anholt2019-04-261-2/+4
| | | | | | We are assured that the input segment size field is ignored for !separate_segs mode, and now the simulator wants an in-range value set regardless of whether it's functionally ignored or not.
* v3d: Disable SSBOs and atomic counters on vertex shaders.Eric Anholt2019-04-241-0/+3
| | | | | | | | | | The CTS fails on dEQP-GLES31.functional.shaders.opaque_type_indexing.atomic_counter.*vertex when they are enabled, due to the VS being run for both bin and render. I think this behavior is expected to be valid, but I can't find text in atomic counters or SSBO specs saying so (the closed I found was in shader_image_load_store). Just disable it for now, since the closed source driver doesn't expose vertex atomic counters/SSBOs either.
* Delete autotoolsDylan Baker2019-04-152-75/+0
| | | | | | | | | | Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Acked-by: Marek Olšák <[email protected]> Acked-by: Jason Ekstrand <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]> Acked-by: Matt Turner <[email protected]>
* v3d: Use the new lower_to_scratch implementation for indirects on temps.Eric Anholt2019-04-121-1/+2
| | | | | | | | | | | | | We can use the same register spilling infrastructure for our loads/stores of indirect access of temp variables, instead of doing an if ladder. Cuts 50% of instructions and max-temps from 2 KSP shaders in shader-db. Also causes several other KSP shaders with large bodies and large loop counts to not be force-unrolled. The change was originally motivated by NOLTIS slightly modifying register pressure in piglit temp mat4 array read/write tests, triggering register allocation failures.
* v3d: Detect the correct number of QPUs and use it to fix the spill size.Eric Anholt2019-04-122-4/+10
| | | | | We were missing a * 4 even if the particular hardware matched our assumption.
* v3d: Add Compute Shader compilation support.Eric Anholt2019-04-126-79/+258
| | | | | | | | While waiting for the CSD UABI to get reviewed, I keep having to rebase the CS patch. Just land the compiler side for now to keep it from diverging. For now this covers just GLES 3.1 compute shaders, not CL kernels.
* v3d: Drop a note for the future about PIPE_CAP_PACKED_UNIFORMS.Eric Anholt2019-04-121-0/+7
|
* nir/i965/freedreno/vc4: add a bindless bool to type size functionsTimothy Arceri2019-04-121-1/+1
| | | | | | | This required to calculate sizes correctly when we have bindless samplers/images. Reviewed-by: Marek Olšák <[email protected]>
* st: Lower uniforms in st in the !PIPE_CAP_PACKED_UNIFORMS case as well.Eric Anholt2019-04-101-11/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | PIPE_CAP_PACKED_UNIFORMS conflates several things: Lowering uniforms i/o at the st level instead of the backend, packing uniforms with no padding at all, and lowering to UBOs. Requiring backends to lower uniforms i/o for !PIPE_CAP_PACKED_UNIFORMS leads to the driver needing to either link against the type size function in mesa/st, or duplicating it in the backend. Given that all backends want this lower-io as far as I can tell, just move it to mesa/st to resolve the link issue and avoid the driver author needing to understand st's uniforms layout. Incidentally, fixes uniform layout failures in nouveau in: dEQP-GLES2.functional.shaders.struct.uniform.sampler_nested_fragment dEQP-GLES2.functional.shaders.struct.uniform.sampler_nested_vertex dEQP-GLES2.functional.shaders.struct.uniform.sampler_array_fragment dEQP-GLES2.functional.shaders.struct.uniform.sampler_array_vertex and I think in Lima as well. v2: fix indents Reviewed-by: Kenneth Graunke <[email protected]>
* nir: Get rid of global registersJason Ekstrand2019-04-091-1/+0
| | | | | | | | | We have a pass to lower global registers to locals and many drivers dutifully call it. However, no one ever creates a global register ever so it's all dead code. It's time we bury it. Acked-by: Karol Herbst <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* v3d: Don't try to use the TFU blit path if a scissor is enabled.Eric Anholt2019-04-041-1/+2
| | | | | | | | We'll need to do a render-based blit for scissors, since the TFU (as seen in this conditional) can only update a whole surface. Fixes: 976ea90bdca2 ("v3d: Add support for using the TFU to do some blits.") Fixes piglit fbo-scissor-blit.
* v3d: Bump the maximum texture size to 4k for V3D 4.x.Eric Anholt2019-04-043-2/+29
| | | | | | | 4.1 and 4.2 both have the same 16k limit, but it I'm seeing GPU hangs in the CTS at 8k and 16k. 4k at least lets us get one 4k display working. Cc: [email protected]
* v3d: Add support for handling OOM signals from the simulator.Eric Anholt2019-04-043-14/+78
| | | | | | I have v3d allocating enough initial allocation memory that we've been passing tests without it, but to match kernel behavior more it would be good to actually exercise the OOM path.
* gallium: add writable_bitmask parameter into set_shader_buffersMarek Olšák2019-04-041-1/+2
| | | | | | | to indicate write usage per buffer. This is just a hint (it will be used by radeonsi). Reviewed-by: Timothy Arceri <[email protected]>
* v3d: Upload all of UBO[0] if any indirect load occurs.Eric Anholt2019-03-211-38/+19
| | | | | | | | | | | | | | | The idea was that we could skip uploading the constant-indexed uniform data and just upload the uniforms that are variably-indexed. However, since the VS bin and render shaders may have a different set of uniforms used, this meant that we had to upload the UBO for each of them. The first case is generally a fairly small impact (usually the uniform array is the most space, other than a couple of FSes in shader-db), while the second is a larger impact: 3DMMES2 was uploading 38k/frame of uniforms instead of 18k. Given that the optimization is of dubious value, has a big downside, and is quite a bit of code, just drop it. No change in shader-db. No change on 3DMMES2 (n=15).
* v3d: Move constant offsets to UBO addresses into the main uniform stream.Eric Anholt2019-03-212-2/+6
| | | | | | | | | | We'd end up with the constant offset in the uniform stream anyway, since they're bigger than small immediates. Avoids the extra uniforms and adds in the shader in favor of just adding once on the CPU. shader-db: total instructions in shared programs: 6496865 -> 6494851 (-0.03%) total uniforms in shared programs: 2119511 -> 2117243 (-0.11%)
* v3d: Rename v3d_tmu_config_data to v3d_unit_data.Eric Anholt2019-03-211-4/+4
| | | | | | I want to reuse this for encoding small constant UBO/SSBO offsets into the uniform stream to reduce the extra uniform loads and adds for the small constant offsets.
* gallium: Add PIPE_BARRIER_UPDATE_BUFFER and UPDATE_TEXTURE bits.Kenneth Graunke2019-03-191-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The glMemoryBarrier() function makes shader memory stores ordered with respect to things specified by the given bits. Until now, st/mesa has ignored GL_TEXTURE_UPDATE_BARRIER_BIT and GL_BUFFER_UPDATE_BARRIER_BIT, saying that drivers should implicitly perform the needed flushing. This seems like a pretty big assumption to make. Instead, this commit opts to translate them to new PIPE_BARRIER bits, and adjusts existing drivers to continue ignoring them (preserving the current behavior). The i965 driver performs actions on these memory barriers. Shader memory stores go through a "data cache" which is separate from the render cache and other read caches (like the texture cache). All memory barriers need to flush the data cache (to ensure shader memory stores are visible), and possibly invalidate read caches (to ensure stale data is no longer visible). The driver implicitly flushes for most caches, but not for data cache, since ARB_shader_image_load_store introduced MemoryBarrier() precisely to order these explicitly. I would like to follow i965's approach in iris, flushing the data cache on any MemoryBarrier() call, so I need st/mesa to actually call the pipe->memory_barrier() callback. Fixes KHR-GL45.shader_image_load_store.advanced-sync-textureUpdate and Piglit's spec/arb_shader_image_load_store/host-mem-barrier on the iris driver. Roland said this looks reasonable to him. Reviewed-by: Eric Anholt <[email protected]>
* v3d: Expose the dma-buf modifiers query.Eric Anholt2019-03-191-0/+29
| | | | | | | | | | This allows DRI3 to pick between UIF and raster according to whether we're pageflipping or not and whether the pageflipping display can do UIF, avoiding copies for the windowed/composited case that previously was forced to linear. Improves windowed glmark2 -b build:use-vbo=false performance by 30.7783% +/- 13.1719% (n=3)
* v3d: Allow the UIF modifier with renderonly.Eric Anholt2019-03-191-38/+52
| | | | | | | We ask the other side to make a buffer with the right number of pages, and then just store the UIF in it. This avoids an extra silent copy of the buffer from linear to UIF if it gets used for texturing (X11 copy-based swapbuffers, GL compositors).
* v3d: Always lay out shared tiled buffers with UIF_TOP set.Eric Anholt2019-03-191-4/+6
| | | | | The samplers are already ready for this, we just needed to make sure that layout chose UIF for level 0.
* v3d: Use shared drm_find_modifier utilAlyssa Rosenzweig2019-03-141-15/+3
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* v3d: Fix leak of the renderonly struct on screen destruction.Eric Anholt2019-03-121-0/+1
| | | | | | This makes v3d match vc4's destroy path. Fixes: e113b21cb779 ("v3d: Add renderonly support.")
* v3d: Disable PIPE_CAP_BLIT_BASED_TEXTURE_TRANSFER.Eric Anholt2019-03-121-0/+3
| | | | | | This reduces the runtime of dEQP-GLES3.functional.shaders.precision.* from 11.5s to 3.3s. This brings CTS runs down to 4 hours on one of my target devices.
* tgsi_to_nir: Produce optimized NIR for a given pipe_screen.Timur Kristóf2019-03-051-1/+1
| | | | | | | | | | | | | | | | | | | With this patch, tgsi_to_nir will output NIR that is tailored to the given pipe, by reading its capabilities and adjusting the NIR code to those capabilities similarly to how glsl_to_nir works. It also adds an optimization loop that brings the output NIR in line with what glsl_to_nir outputs. This is necessary for the same reason why glsl_to_nir has its own optimization loop: currently not every driver does these optimizations yet. For uses which cannot pass a pipe_screen we also keep a variant called tgsi_to_nir_noscreen which keeps the old behavior. Signed-Off-By: Timur Kristóf <[email protected]> Tested-by: Andre Heider <[email protected]> Tested-by: Rob Clark <[email protected]> Acked-By: Eric Anholt <[email protected]>
* v3d: Fix build of NEON code with Mesa's cflags not targeting NEON.Eric Anholt2019-03-011-3/+17
| | | | | | | | v3d may be built as part of a set of drivers in a system not requiring NEON, but we know V3D devices will be paired with CPUs with NEON so we should be able to use this asm. Fixes: 0c05198d6b5b ("v3d: Always enable the NEON utile load/store code.")
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-27 21:59:56 +0000