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* radeonsi: fix CMASK and HTILE allocation on TahitiMarek Olšák2014-08-091-1/+54
| | | | | | | | | | | | | | | | Tahiti has 12 tile pipes, but P8 pipe config. It looks like there is no way to get the pipe config except for reading GB_TILE_MODE. The TILING_CONFIG ioctl doesn't return more than 8 pipes, so we can't use that for Hawaii. This fixes a regression caused by 9b046474c95f15338d4c748df9b62871bba6f36f on Tahiti. v2: add an assertion and print an error on failure Cc: [email protected] Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: use gpu_address from r600_resourceMarek Olšák2014-08-096-56/+41
| | | | | Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: always prefer SWITCH_ON_EOP(0) on CIKMarek Olšák2014-08-091-9/+24
| | | | | | | | | | | | | | The code is rewritten to take known constraints into account, while always using 0 by default. This should improve performance for multi-SE parts in theory. A debug option is also added for easier debugging. (If there are hangs, use the option. If the hangs go away, you have found the problem.) Reviewed-by: Alex Deucher <[email protected]> v2: fix a typo, set max_se for evergreen GPUs according to the kernel driver
* radeonsi: fix a hang with instancing in Unigine Heaven/Valley on HawaiiMarek Olšák2014-08-091-5/+2
| | | | | | | | This isn't documented anywhere, but it's the only thing that works for this case. Cc: [email protected] Reviewed-by: Alex Deucher <[email protected]>
* gallium/radeon: Add some Emacs .dir-locals.el filesMichel Dänzer2014-07-291-0/+11
| | | | | | Based on the toplevel one but adapted to the driver/winsys coding styles. Reviewed-by: Marek Olšák <[email protected]>
* r600g,radeonsi: switch all occurences of array_size to util_max_layerMarek Olšák2014-07-281-1/+1
| | | | | | | | | | | | | | | | | | This fixes 3D texture support in all these cases, because array_size is 1 with 3D textures and depth0 actually contains the "array size". util_max_layer is universal and returns the last layer index for any texture target. A lot of the cases below can't actually be hit with 3D textures, but let's be consistent. This fixes a failure in: piglit layered-rendering/clear-color-all-types 3d single_level for r600g and radeonsi, which was caused by an incorrect CMASK size calculation. Cc: [email protected] Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: fix a hang with streamout on HawaiiMarek Olšák2014-07-281-1/+13
| | | | | | | | | | | I actually couldn't reproduce this one, but internal docs recommend this workaround. Better safe than sorry. Also, the number of dwords for the sync packets is increased by 4 instead of 2, because it wasn't bumped last time when a new packet was added there. Cc: [email protected] Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: fix a hang with instancing on HawaiiMarek Olšák2014-07-281-1/+15
| | | | | | | This fixes "piglit/bin/arb_transform_feedback2-draw-auto instanced". Cc: [email protected] Reviewed-by: Alex Deucher <[email protected]>
* gallium: rename shader cap MAX_CONSTS to MAX_CONST_BUFFER_SIZEMarek Olšák2014-07-281-2/+2
| | | | | | | | | | This new name isn't so confusing. I also changed the gallivm limit, because it looked wrong. Reviewed-by: Brian Paul <[email protected]> v2: use sizeof(float[4])
* radeonsi: Use util_memcpy_cpu_to_le32()Tom Stellard2014-07-282-19/+8
| | | | Reviewed-by: Marek Olšák <[email protected]>
* r600g/radeonsi: Use write-combined CPU mappings of some BOs in GTTMichel Dänzer2014-07-231-1/+1
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/compute: Add support scratch buffer support v2Tom Stellard2014-07-213-2/+85
| | | | | | | | The scratch buffer will be used for private memory and also register spilling. v2: - Code cleanups
* radeonsi/compute: Bump number of user sgprs for LLVM 3.5Tom Stellard2014-07-211-1/+6
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/compute: Share COMPUTE_DBG macro with r600gTom Stellard2014-07-211-0/+5
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Read rodata from ELF and append it to the end of shadersTom Stellard2014-07-211-1/+12
| | | | | | | The is used for programs that have arrays of constants that are accessed using dynamic indices. The shader will compute the base address of the constants and then access them using SMRD instructions.
* radeonsi: only update vertex buffers when they need updatingMarek Olšák2014-07-183-2/+22
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: remove nr_vertex_buffersMarek Olšák2014-07-183-6/+23
| | | | | | | | Unused. Also inline util_set_vertex_buffers_count and simplify it. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: move vertex buffer descriptors from IB to memoryMarek Olšák2014-07-187-106/+133
| | | | | | | | | | This removes the intermediate storage (pm4 state) and generates descriptors directly in a staging buffer. It also reduces the number of flushes, because the descriptors no longer take CS space. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: add support for fine-grained sampler view updatesMarek Olšák2014-07-183-30/+21
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: move si_set_sampler_views to si_descriptors.cMarek Olšák2014-07-183-73/+68
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: move sampler descriptors from IB to memoryMarek Olšák2014-07-185-82/+82
| | | | | | | | | | | | | | Sampler descriptors are now represented by si_descriptors. This also adds support for fine-grained sampler state updates and the border color update is now isolated in a separate function. Border colors have been broken if texturing from multiple shader stages is used. This patch doesn't change that. BTW, blitting already makes use of fine-grained state updates. u_blitter uses 2 textures at most, so we only have to save 2. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: implement ARB_draw_indirectMarek Olšák2014-07-185-17/+128
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: don't add info->start to the index buffer offsetMarek Olšák2014-07-181-11/+25
| | | | | | | info->start will be invalid once info->indirect isn't NULL, so it shouldn't be added to ib.offset. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: use an SGPR instead of VGT_INDX_OFFSETMarek Olšák2014-07-184-14/+23
| | | | | | | | The draw indirect packets cannot set VGT_INDX_OFFSET, they can only set user data SGPRs. This is the only way to support start/index_bias with indirect drawing. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: assume LLVM 3.4.2 is always presentMarek Olšák2014-07-185-49/+7
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: partially revert "switch descriptors to i32 vectors"Marek Olšák2014-07-141-0/+12
| | | | It indeed breaks LLVM 3.4.2.
* radeonsi: rename definitions of shader limitsMarek Olšák2014-07-117-44/+57
| | | | Reviewed-by: Tom Stellard <[email protected]>
* radeonsi: switch descriptors to i32 vectorsMarek Olšák2014-07-111-13/+16
| | | | | | This is a follow-up to the commit which adds texture fetches with offsets. Reviewed-by: Tom Stellard <[email protected]>
* radeonsi: properly implement texture opcodes that take an offsetMarek Olšák2014-07-111-84/+104
| | | | | | | | | | | | Instead of using intr_name in lp_build_tgsi_action, this selects the names with a switch statement in the emit function. This allows emitting llvm.SI.sample for instructions without offsets and llvm.SI.image.sample.*.o otherwise. This depends on my LLVM changes. When LLVM 3.5 is released, I'll switch all texture instructions to the new intrinsics.
* radeonsi: fix texture fetches with derivatives for 1DArray and 3D texturesMarek Olšák2014-07-111-4/+30
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* radeonsi: fix samplerCubeShadow with biasMarek Olšák2014-07-111-6/+6
| | | | | | Pack the depth value before overwriting it with cube coordinates. Cc: [email protected]
* gallium: switch dedicated centroid field to interpolation locationIlia Mirkin2014-07-091-3/+3
| | | | | | | | The new location field can be either center, centroid, or sample, which indicates the location that the shader should interpolate at. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* radeonsi: fix order of r600_need_dma_space and r600_context_bo_relocChristian König2014-07-091-1/+2
| | | | | Signed-off-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: mark MSAA config state as dirty at the beginning of CSMarek Olšák2014-07-081-0/+1
| | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=81020 Reviewed-by: Alex Deucher <[email protected]>
* gallium: rename PIPE_CAP_TGSI_VS_LAYER to also have _VIEWPORTIlia Mirkin2014-07-031-1/+1
| | | | | | | | | Now that this cap is used to determine the availability of both, adjust its name to reflect the new reality. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* Revert "radeonsi: Use dma_copy when possible for si_blit."Michel Dänzer2014-07-031-19/+0
| | | | | | | This reverts commit 5d5c20920e0e570742a497aa047e99a2fa3c04f2. Caused visual corruption, see e.g. https://bugs.freedesktop.org/show_bug.cgi?id=80827#c1
* gallium: Add PIPE_SHADER_CAP_DOUBLESTom Stellard2014-07-021-0/+5
| | | | | | | This is for reporting whether or not double precision floating-point operations are supported. Reviewed-by: Francisco Jerez <[email protected]>
* gallium: add a cap for max vertex streamsIlia Mirkin2014-07-011-0/+2
| | | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* radeonsi: Use dma_copy when possible for si_blit.Axel Davy2014-07-011-0/+19
| | | | | | | | | | | | This improves GLX DRI3 GPU offloading significantly on CPU bound benchmarks particularly. No performance impact for DRI2 GPU offloading. v2: Add missing tests Signed-off-by: Axel Davy <[email protected]> Reviewed-by: Marek Olšák<[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: implement ARB_texture_query_lodMarek Olšák2014-06-192-25/+40
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: pass ARB_conservative_depth parameters to the hardwareMarek Olšák2014-06-194-1/+29
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: cosmetic changes in si_shader.cMarek Olšák2014-06-191-18/+13
| | | | reviewed by Michel Dänzer
* radeonsi: implement ARB_texture_gather and Gather functions from GLSL 4.00Marek Olšák2014-06-192-12/+123
| | | | | | All ARB_texture_gather and gather-related ARB_gpu_shader5 piglit tests pass. reviewed by Michel Dänzer
* radeonsi: add sampling of 4:2:2 subsampled texturesGrigori Goronzy2014-06-182-37/+69
| | | | | | This makes 4:2:2 video surfaces work in VDPAU. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: fixup sizes of shader resource and sampler arraysMarek Olšák2014-06-161-2/+2
| | | | | | | This was wrong for a very long time. I wonder if the array size has any effect on anything. Reviewed-by: Christian König <[email protected]>
* r600g,radeonsi: don't use hardware MSAA resolve if dst is fast-clearedMarek Olšák2014-06-031-1/+2
| | | | | | | It doesn't work and our docs say so too. Cc: [email protected] Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: BlitFramebuffer should follow render conditionMarek Olšák2014-06-031-5/+6
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: enable ARB_sample_shadingMarek Olšák2014-06-021-1/+1
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* radeonsi: implement SAMPLEMASK fragment shader outputMarek Olšák2014-06-021-3/+15
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* radeonsi: interpolate varyings at sample when full sample shading is enabledMarek Olšák2014-06-023-12/+15
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