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path: root/src/gallium/drivers/radeonsi
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* util/u_queue: add UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITYMarek Olšák2018-10-061-1/+3
* radeonsi: fix a typo at CS_PARTIAL_FLUSHMarek Olšák2018-10-061-1/+1
* ac: add ac_build_roundMarek Olšák2018-10-061-3/+1
* ac: correct PKT3_COPY_DATA definitionsMarek Olšák2018-10-064-6/+6
* ac: define all address spaces properlyMarek Olšák2018-10-061-3/+3
* radeonsi:optimizing SET_CONTEXT_REG for shaders vgt_vertex_reuseSonny Jiang2018-10-054-2/+18
* radeonsi:optimizing SET_CONTEXT_REG for shaders TessellationSonny Jiang2018-10-054-5/+26
* radeonsi:optimizing SET_CONTEXT_REG for shaders PSSonny Jiang2018-10-053-14/+60
* radeonsi:optimizing SET_CONTEXT_REG for shaders VSSonny Jiang2018-10-053-33/+77
* radeonsi:optimizing SET_CONTEXT_REG for shaders GSSonny Jiang2018-10-054-24/+154
* radeonsi: optimize and allow reg > 31 in radeon_opt_set_context_reg functionsMarek Olšák2018-10-051-22/+12
* radeonsi: optimizing SET_CONTEXT_REG for shaders ESSonny Jiang2018-10-055-10/+37
* radeonsi: use build-id when available for disk cacheTimothy Arceri2018-10-031-12/+9
* radeonsi: avoid sending GS_EMIT in shaders without outputsJózef Kucia2018-10-021-3/+6
* radeonsi: initialize ac_gpu_info::name when using SI_FORCE_FAMILYMarek Olšák2018-10-021-0/+1
* radeonsi: don't set the VS prolog key for the blit VSMarek Olšák2018-10-021-1/+2
* radeonsi: add a workaround for bitfield_extract when count is 0Timothy Arceri2018-10-021-11/+30
* radeonsi: NaN should pass kill_ifAxel Davy2018-09-251-1/+2
* Revert "radeonsi: avoid syncing the driver thread in si_fence_finish"Timothy Arceri2018-09-182-44/+40
* radeonsi/nir: port some bindless and sampler code from TGSIMarek Olšák2018-09-101-30/+50
* radeonsi: split si_copy_bufferMarek Olšák2018-09-105-17/+33
* radeonsi: don't call VBO prefetch with size=0Marek Olšák2018-09-101-1/+1
* radeonsi: merge SI and CI dma_clear_buffer and remove the callbackMarek Olšák2018-09-107-88/+65
* radeonsi: fix GPU hangs with bindless textures and LLVM 7.0Marek Olšák2018-09-103-5/+33
* ac: use iN_0/1 constantsMarek Olšák2018-09-102-3/+3
* ac: add radeon_info::num_good_cu_per_shMarek Olšák2018-09-101-3/+1
* radeonsi: fix printing a BO list into ddebug reportsMarek Olšák2018-09-101-1/+2
* radeonsi: fix HTILE for NPOT textures with mipmapping on SI/CIMarek Olšák2018-09-101-2/+2
* gallium: add PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGETMarek Olšák2018-09-071-0/+4
* radeonsi: pin the winsys thread to the requested L3 cache (v2)Marek Olšák2018-09-071-0/+15
* gallium: enable GL_AMD_depth_clamp_separate on r600, radeonsiMarek Olšák2018-09-062-1/+2
* gallium: split depth_clip into depth_clip_near & depth_clip_farMarek Olšák2018-09-061-2/+2
* nir: Drop the vs_inputs_dual_locations optionJason Ekstrand2018-09-061-1/+0
* radeonsi/nir: Set vs_inputs_dual_locations and let NIR do the remapJason Ekstrand2018-09-061-0/+1
* gallium: add PIPE_CAP_RASTERIZER_SUBPIXEL_BITSMarek Olšák2018-09-061-0/+1
* gallium: Add a helper for implementing PIPE_CAP_* default values.Eric Anholt2018-09-041-1/+4
* radeonsi: fix regression in indirect input swizzles.Dave Airlie2018-08-311-2/+5
* radeonsi: fix tess/gs fetchs for new swizzle.Dave Airlie2018-08-311-5/+8
* gallivm: allow to pass two swizzles into fetches.Dave Airlie2018-08-302-11/+14
* radeonsi: add radeonsi_zerovram driconfig optionTimothy Arceri2018-08-301-0/+1
* radeonsi: enable GL 4.5 in compat profileTimothy Arceri2018-08-301-2/+1
* radeonsi: add a thorough clear/copy_buffer benchmarkMarek Olšák2018-08-299-153/+599
* radeonsi: let internal compute dispatches tune WAVES_PER_SHMarek Olšák2018-08-292-0/+9
* radeonsi: add TGSI_SEMANTIC_CS_USER_DATA for reading up to 4 SGPRs with TGSIMarek Olšák2018-08-296-3/+34
* radeonsi: add SI_QUERY_TIME_ELAPSED_SDMA_SI for measuring DMA on SIMarek Olšák2018-08-292-0/+20
* radeonsi: add SI_QUERY_TIME_ELAPSED_SDMA for measuring SDMA performanceMarek Olšák2018-08-294-2/+51
* radeonsi: add flag L2_STREAM for minimal cache usageMarek Olšák2018-08-292-6/+11
* gallium: add TGSI_MEMORY_STREAM_CACHE_POLICYMarek Olšák2018-08-291-0/+3
* gallium: Split out PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE.Kenneth Graunke2018-08-241-0/+1
* Revert "configure: allow building with python3"Emil Velikov2018-08-241-1/+1
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