summaryrefslogtreecommitdiffstats
path: root/src/gallium/drivers/radeonsi
Commit message (Expand)AuthorAgeFilesLines
* radeonsi: log draw and compute state into log contextNicolai Hähnle2017-08-224-32/+51
* radeonsi: print saved CS to the log contextNicolai Hähnle2017-08-225-88/+263
* radeonsi: start using u_log_context for debuggingNicolai Hähnle2017-08-221-64/+175
* radeonsi: re-order debug state dumpingNicolai Hähnle2017-08-221-7/+8
* radeonsi: make si_shader_selector_reference globally visibleNicolai Hähnle2017-08-222-15/+16
* radeonsi: add reference count to si_computeNicolai Hähnle2017-08-222-10/+28
* radeonsi: implement pipe_context::set_log_contextNicolai Hähnle2017-08-221-0/+9
* radeonsi: don't prefetch VBO descriptors if vertex elements == NULLMarek Olšák2017-08-212-1/+4
* Android: Fix LLVM duplicated symbols linking for N and MRob Herring2017-08-211-1/+1
* radeon/uvd: add YUYV format support for target bufferLeo Liu2017-08-211-1/+1
* radeonsi: update non-resident bindless descriptors if neededSamuel Pitoiset2017-08-211-30/+55
* gallium/radeon: remove old_fence parameter from r600_gfx_write_event_eopMarek Olšák2017-08-182-3/+2
* radeonsi/gfx9: prevent a GPU hang after a timestamp eventMarek Olšák2017-08-182-3/+3
* radeonsi: don't use CLEAR_STATE on SIMarek Olšák2017-08-184-10/+63
* radeonsi: disable CE by defaultMarek Olšák2017-08-151-6/+18
* radeonsi/gfx9: fix the scissor bug workaroundMarek Olšák2017-08-111-3/+7
* radeonsi/gfx9: use the VI codepath for clamping ZMarek Olšák2017-08-112-12/+2
* ac: fail shader compilation if libelf is replaced by an incompatible versionMarek Olšák2017-08-101-1/+4
* radeonsi: drop two unused variables in create_function()Samuel Pitoiset2017-08-091-2/+0
* radeonsi: fix a compile failure due to disabled assertsMarek Olšák2017-08-071-1/+1
* radeonsi: use optimal packet order when doing a pipeline syncMarek Olšák2017-08-071-34/+83
* radeonsi: expose the number of decompress calls to the HUDMarek Olšák2017-08-071-7/+11
* radeonsi: rename shader_userdata -> shader_pointers where appropriateMarek Olšák2017-08-075-20/+20
* radeonsi: prefetch VBO descriptors after the first VGT shaderMarek Olšák2017-08-071-17/+63
* radeonsi: add a separate dirty mask for prefetchesMarek Olšák2017-08-076-16/+64
* radeonsi: add and use si_pm4_state_enabled_and_changedMarek Olšák2017-08-073-17/+18
* radeonsi: de-atomize L2 prefetchMarek Olšák2017-08-077-9/+11
* radeonsi: align all CE dumps to L2 cache line sizeMarek Olšák2017-08-071-8/+17
* radeonsi: remove a tautology sctx->framebuffer.nr_samples >= 1Marek Olšák2017-08-071-2/+1
* radeonsi: enable support for EXT_memory_objectAndres Rodriguez2017-08-061-1/+1
* radeonsi: hook up device/driver UUID queriesAndres Rodriguez2017-08-061-0/+14
* android: radeonsi: add nir include pathsMauro Rossi2017-08-041-1/+2
* radeonsi: set drirc compiler options before calling common screen initNicolai Hähnle2017-08-041-4/+10
* radeonsi: Makefile.sources: include driinfo_radeonsi.hJuan A. Suarez Romero2017-08-041-0/+1
* radeonsi: program tile swizzle for color and FMASK surfaces for GFX & SDMAMarek Olšák2017-08-043-3/+29
* radeonsi: if FMASK is disabled, set CB_COLORi_FMASK = CB_COLORi_BASE properlyMarek Olšák2017-08-041-1/+5
* android: radeonsi: prepare for driver-specific driconf optionsMauro Rossi2017-08-031-0/+17
* gallium: introduce PIPE_CAP_MEMOBJTimothy Arceri2017-08-031-0/+1
* radeonsi: add enable_sisched driconf optionNicolai Hähnle2017-08-022-0/+7
* radeonsi: prepare for driver-specific driconf optionsNicolai Hähnle2017-08-023-0/+18
* gallium: add pipe_screen_config to screen_create functionsNicolai Hähnle2017-08-022-3/+3
* radeonsi: enable ARB_transform_feedback_overflow_queryNicolai Hähnle2017-08-021-1/+1
* gallium: add PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE and corresponding capNicolai Hähnle2017-08-021-0/+1
* radeon/ac: use ds_swizzle for derivs on si/cik.Dave Airlie2017-08-021-15/+1
* radeonsi: print CE IBs into ddebug reportsMarek Olšák2017-08-014-6/+34
* radeonsi: fix printing vertex buffer descriptors into ddebug reportsMarek Olšák2017-08-012-0/+8
* radeonsi: don't flush sL1 conditionally in WAIT_ON_CE_COUNTERMarek Olšák2017-08-011-3/+3
* radeonsi: set up HTILE in descriptors only when level 0 is accessibleMarek Olšák2017-08-011-1/+1
* radeonsi: fix various CLEAR_STATE issuesMarek Olšák2017-08-011-0/+22
* radeonsi: ensure that temp array allocas are in the entry blockNicolai Hähnle2017-07-311-1/+1