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* radeonsi/compute: Enable PIPE_SHADER_CAP_DOUBLES v2Tom Stellard2015-02-271-2/+2
| | | | | | | v2: - Simplify ifdef Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: small cleanup around current_rast_primMarek Olšák2015-02-241-9/+6
| | | | | | | | - remove the last parameter of si_emit_rasterizer_prim_state - remove the last unused parameter of si_emit_draw_registers - use current_rast_prim in si_emit_draw_registers Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: set current_rast_prim in the right placeMarek Olšák2015-02-241-1/+7
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: simplify obtaining a shader property in si_emit_clip_regsMarek Olšák2015-02-241-2/+1
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: only preload VertexID for the GS copy shaderMarek Olšák2015-02-241-4/+6
| | | | | | The copy shader doesn't use any other preloaded VGPRs. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: dump the shader key when dumping shadersMarek Olšák2015-02-241-0/+38
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* r600g,radeonsi: cleanup of hex literalsMarek Olšák2015-02-241-16/+16
| | | | | | | | 0x3F800000 -> fui(1.0) 0x00000000 -> 0 Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: set PA_SU_HARDWARE_SCREEN_OFFSET to 0Marek Olšák2015-02-241-0/+2
| | | | | | It was probably 0 already, but it doesn't hurt to set it. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: fix a warning caused by previous commitMarek Olšák2015-02-231-1/+1
| | | | Cc: 10.5 10.4 <[email protected]>
* radeonsi: fix point spritesMarek Olšák2015-02-231-1/+1
| | | | | | | | Broken by a27b74819ad375e8c0bc88e13f42c951d2b5cd6a. This fix is critical and should be ported to stable ASAP. Cc: 10.5 10.4 <[email protected]>
* radeonsi: don't use SQC_CACHES to flush ICACHE and KCACHE on SIMarek Olšák2015-02-201-18/+11
| | | | | | | | | | | | | | | This reverts 73c2b0d18c51459697d8ec194ecfc4438c98c139. It doesn't seem to be reliable. It's probably missing a wait packet or something, because it's just a register write and doesn't wait for anything. SURFACE_SYNC at least seems to wait until the flush is done. Just guessing. Let's not complicate things and revert this. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88561 Cc: 10.5 <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* gallium: add shader cap for dldexp/dfracexp supportIlia Mirkin2015-02-191-0/+1
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* gallium: add a cap to enable double rounding opcodesIlia Mirkin2015-02-191-0/+1
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radeonsi: fix a crash if a stencil ref state is set before a DSA stateMarek Olšák2015-02-171-4/+8
| | | | | | | | | | | | + minor indentation fixes Discovered by Axel Davy. This can't be reproduced with any app, because all state trackers set a DSA state first. Cc: 10.5 10.4 10.3 <[email protected]> Reviewed-by: Axel Davy <[email protected]>
* r600g,radeonsi: implement GL_AMD_pinned_memoryMarek Olšák2015-02-171-0/+3
| | | | | | v2: update release notes Reviewed-by: Christian König <[email protected]>
* radeonsi: small fix in SPI stateMarek Olšák2015-02-171-2/+4
| | | | | Cc: 10.5 10.4 <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* gallium: Add MULTISAMPLE_Z_RESOLVE capAxel Davy2015-02-061-0/+1
| | | | | | | | | | | | | | | | Resolving a multisampled depth texture into a single sampled texture is supported on >= SM4.1 hw. It is possible some previous hw support it. The ability was tested on radeonsi and nvc0. Apparently is is also supported for radeon >= r700. This patch adds the MULTISAMPLE_Z_RESOLVE cap and add it to the drivers. It is advertised for drivers for which it is sure the ability is supported. Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Axel Davy <[email protected]>
* radeonsi: implement polygon stipplingMarek Olšák2015-02-047-5/+79
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: add polygon stipple texture slotMarek Olšák2015-02-041-5/+8
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: deduce rasterizer primitive type at the beginning of draw_vboMarek Olšák2015-02-042-13/+17
| | | | | | I will need this for polygon stippling. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: allow 64 descriptors per arrayMarek Olšák2015-02-042-34/+34
| | | | | | | We need a slot for the stipple texture and the pixel shader already uses 32 textures (16 API slots + 16 FMASK slots). Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: add support for sampler views where resource = NULLMarek Olšák2015-02-042-6/+22
| | | | | | | The hardware obeys swizzles even if the resource is NULL. This will be used by set_polygon_stipple. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: add support for NULL texture sampler views that return (0,0,0,1)Marek Olšák2015-02-041-2/+28
| | | | | | This used to hang. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: fix a crash when binding a NULL sampler view listMarek Olšák2015-02-041-1/+1
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: move the buffer descriptor to the end of the image descriptorMarek Olšák2015-02-044-7/+9
| | | | | | This will allow supporting NULL textures. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: don't use tgsi_parse_context to get processor typeMarek Olšák2015-02-041-7/+1
| | | | | | Also remove unused "tokens". Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: fix instanced arrays with non-zero start instanceMarek Olšák2015-02-041-3/+3
| | | | | | | Fixes piglit ARB_base_instance/arb_base_instance-drawarrays. Cc: 10.3 10.4 <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* gallium: add a cap to determine whether the driver supports offset_clampIlia Mirkin2015-02-021-0/+1
| | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Glenn Kennard <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* dir-locals.el: Don't set variables for non-programming modesNeil Roberts2015-02-021-1/+1
| | | | | | | | | | | | | | This limits the style changes to modes inherited from prog-mode. The main reason to do this is to avoid setting fill-column for people using Emacs to edit commit messages because 78 characters is too many to make it wrap properly in git log. Note that makefile-mode also inherits from prog-mode so the fill column should continue to apply there. v2: Apply to all the .dir-locals.el files, not just the one in the root directory. Acked-by: Michel Dänzer <[email protected]>
* radeonsi: Enable VGPR spilling for all shader types v5Tom Stellard2015-01-288-52/+217
| | | | | | | | | | | | | | | | | | | | v2: - Only emit write SPI_TMPRING_SIZE once per packet. - Use context global scratch buffer. v3: - Patch shaders using WRITE_DATA packet instead of map/unmap. - Emit ICACHE_FLUSH, CS_PARTIAL_FLUSH, PS_PARTIAL_FLUSH, and VS_PARTIAL_FLUSH when patching shaders. v4: - Code cleanups. - Remove unnecessary multiplies. v5: - Patch shaders in system memory and re-upload to vram. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi/compute: Allocate the scratch buffer during state creationTom Stellard2015-01-282-24/+62
| | | | | | | | | | This moves scratch buffer allocation from si_launch_grid() to si_create_compute_state(). This helps to reduce the overhead of launching a kernel and also fixes a bug in the code that would cause the scratch buffer to be too small if a kernel with smaller scratch size was launched before a kernel with a larger scratch size. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: Add radeon_shader_binary member to struct si_shaderTom Stellard2015-01-282-6/+6
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi/compute: Rename si_compute::program to si_compute::shaderTom Stellard2015-01-281-5/+5
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: Avoid leaking memory when rebuilding shader statesMarek Olšák2015-01-283-4/+13
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi/compute: Use relocs for scratch pointer rather than user sgprs v2Tom Stellard2015-01-201-0/+42
| | | | | | | | | Instead of passing a pointer to the scratch buffer via user sgprs, we now patch the shader with the buffer address using reloc information from the LLVM generated ELF. v2: - Make sure not to break older LLVM.
* radeon: Teach radeon_elf_read() how to parse reloc information v3Tom Stellard2015-01-202-2/+2
| | | | | | | | | v2: - Use strdup for copying reloc names. - Free reloc memory. v3: - Add free_relocs parameter to radeon_shader_binary_free_members()
* radeon: Add a helper function for freeing members of radeon_shader_binaryTom Stellard2015-01-202-6/+2
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* Revert "radeonsi: only set BC_OPTIMIZE_DISABLE when necessary"Michel Dänzer2015-01-152-15/+6
| | | | | | | | | | | | | | | | This reverts commit 0543630d0b0d9d9f6eefbc14fbd3385d4de37ba0. It caused flickering artifacts in Steam games such as Team Fortress 2 or Left 4 Dead 2. We could probably only enable this optimization by also making sure the shader code only uses either SI_PARAM_LINEAR_CENTROID or SI_PARAM_LINEAR_CENTER, not both. This would probably require a shader variant. Sorry I didn't remember this when reviewing the reverted change. Reviewed-by: Marek Olšák <[email protected]>
* Revert "radeonsi: reduce the size of si_pm4_state"Marek Olšák2015-01-082-3/+12
| | | | | | This reverts commit 9141d8855555e45a057970e78969e1518ad3617d. It broke OpenCL.
* radeonsi: Fix crash when destroying si_screenTom Stellard2015-01-071-2/+4
| | | | | | | | | We were invalidating si_screen:tm by calling r600_destroy_common_screen() which frees the si_screen object. This caused the driver to crash in LLVMDisposeTargetMachine() since we were passing it an invalid pointer. https://bugs.freedesktop.org/show_bug.cgi?id=88170
* radeonsi: enable LLVM optimizations that assume no NaNs for non-compute shadersMarek Olšák2015-01-073-4/+12
| | | | | | | v2: complete rewrite Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeonsi: emit SURFACE_SYNC lastMarek Olšák2015-01-071-23/+35
| | | | | | | This fixes a case where a transform feedback buffer is fed back as an index buffer, because SURFACE_SYNC must be after VS_PARTIAL_FLUSH. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: flush all CB/DB caches unconditionally when changing the framebufferMarek Olšák2015-01-071-11/+7
| | | | | | This is easier to read and will work better with shader image stores. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: change TC cache flushing strategy for texturesMarek Olšák2015-01-072-4/+6
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: improve and fix streamout flushingMarek Olšák2015-01-073-10/+40
| | | | | | | | | | | - we don't usually need to flush TC L2 - we should flush KCACHE (not really an issue now since we always flush KCACHE when updating descriptors, but it could be a problem if we used CE, which doesn't require flushing KCACHE) - add an explicit VS_PARTIAL_FLUSH flag Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: use TC L2 for CP DMA operations with shader resources on CIKMarek Olšák2015-01-072-10/+27
| | | | | | | | | So that TC L2 doesn't need to be flushed. The only problem is with index buffers, which don't use TC. A simple solution is added that flushes TC L2 before a draw call (TC_L2_dirty). Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: use TC L2 for updating descriptors on CIKMarek Olšák2015-01-072-5/+10
| | | | | | This allows not flushing TC L2 on CIK later. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: don't use TC L2 for updating descriptors on SIMarek Olšák2015-01-072-2/+14
| | | | | | | | | | | | It's causing problems, because we mix uncached CP DMA with cached WRITE_DATA when updating the same memory. The solution for SI is to use uncached access here, because CP DMA doesn't support cached access. CIK will be handled in the next patch. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: only flush the right set of caches for CP DMA operationsMarek Olšák2015-01-074-25/+32
| | | | | | | | That's either framebuffer caches or caches for shader resources. The motivation is that framebuffer caches need to be flushed very rarely here. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: implement separate ICACHE and KCACHE flush for SIMarek Olšák2015-01-071-9/+17
| | | | Reviewed-by: Michel Dänzer <[email protected]>
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