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* radeonsi: use ac_build_buffer_load for shader buffer loadsMarek Olšák2017-05-291-22/+21
| | | | | | and document why we can't use SMEM yet. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move building llvm.SI.load.const into ac_build_buffer_loadMarek Olšák2017-05-291-13/+10
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: rename readonly_memory -> can_speculateMarek Olšák2017-05-292-14/+14
| | | | | | | This is more accurate. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: fix a crash in si_destroy_context if we fail earlyMarek Olšák2017-05-291-1/+2
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: drop useless memcmp() check in si_set_blend_color()Samuel Pitoiset2017-05-271-3/+0
| | | | | | | | | cso_set_blend_color() already checks if the old state is different. Only Nine uses pipe::set_blend_color() directly but I guess it should use the cache too. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: enable vcn decodeLeo Liu2017-05-251-1/+4
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon: rename has_uvd info to has_hw_decodeLeo Liu2017-05-251-1/+1
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeonsi/gfx9: compile shaders with +xnackMarek Olšák2017-05-221-6/+7
| | | | | | | so that LLVM doesn't allocate SGPRs where XNACK is. Cc: 17.1 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: use CE RAM optimallyMarek Olšák2017-05-182-36/+134
| | | | | | | | | | | | | | On GFX9 with only 4K CE RAM, define the range of slots that will be allocated in CE RAM. All other slots will be uploaded directly. This will switch dynamically according to which slots are used by current shaders. GFX9 CE usage should now be similar to VI instead of being often disabled. Tested on VI by taking the GFX9 CE allocation codepath and setting num_ce_slots = 2 everywhere to get frequent switches between both modes. CE is still disabled on GFX9. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove CE offset alignment restrictionMarek Olšák2017-05-181-2/+1
| | | | | | | This was only needed by LOAD_CONST_RAM, which is now only used to load whole CE. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: only upload (dump to L2) those descriptors that are used by shadersMarek Olšák2017-05-184-24/+117
| | | | | | | This decreases the size of CE RAM dumps to L2, or the size of descriptor uploads without CE. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: record which descriptor slots are used by shadersMarek Olšák2017-05-185-0/+41
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: update si_ce_needed_cs_spaceMarek Olšák2017-05-181-8/+8
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: do only 1 big CE dump at end of IBs and one reload in the preambleMarek Olšák2017-05-185-37/+37
| | | | | | | | A later commit will only upload descriptors used by shaders, so we won't do full dumps anymore, so the only way to have a complete mirror of CE RAM in memory is to do a separate dump after the last draw call. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove early return in si_upload_descriptorsMarek Olšák2017-05-181-3/+0
| | | | | | | | All updates of descriptors_dirty also set dirty_mask, so the return is unnecessary. The next commit will want this function to be executed even if dirty_mask == 0. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: clamp indirect index to the number of declared shader resourcesMarek Olšák2017-05-184-4/+15
| | | | | | | We'll do partial uploads of descriptor arrays, so we need to clamp against what shaders declare. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: merge sampler and image descriptor lists into oneMarek Olšák2017-05-186-112/+99
| | | | | | | | | | | | Sampler slots: slot[8], .. slot[39] (ascending) Image slots: slot[7], .. slot[0] (descending) Each image occupies 1/2 of each slot, so there are 16 images in total, therefore the layout is: slot[15], .. slot[0]. (in 1/2 slot increments) Updating image slot 2n+i (i <= 1) also dirties and re-uploads slot 2n+!i. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: merge constant and shader buffers descriptor lists into oneMarek Olšák2017-05-188-132/+152
| | | | | | | | | | Constant buffers: slot[16], .. slot[31] (ascending) Shader buffers: slot[15], .. slot[0] (descending) The idea is that if we have 4 constant buffers and 2 shader buffers, we only have to upload 6 slots. That optimization is left for a later commit. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: get the sampler view type from inst->Texture for TG4Samuel Pitoiset2017-05-181-7/+3
| | | | | | | | | This will also magically fix this special lowering for bindless samplers. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium: add PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTIONMarek Olšák2017-05-171-0/+1
| | | | | | for skipping mapped-buffer checking in every GL draw call Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: extract TGSI memory/texture opcode handling into its own fileNicolai Hähnle2017-05-165-1841/+1886
| | | | | | It's about time to get the growth of si_shader.c somewhat under control. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: make const_array externally accessibleNicolai Hähnle2017-05-162-13/+15
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: make get_bounded_indirect_index externally accessibleNicolai Hähnle2017-05-162-16/+20
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: make emit_waitcnt externally accessibleNicolai Hähnle2017-05-162-10/+12
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: silence a Coverity warningNicolai Hähnle2017-05-161-0/+2
| | | | | | | | | | | | Coverity doesn't understand that we'll never pass non-NULL for vertex shaders. This is a bit lame, actually. A straightforward cross-procedural analysis limited to this source file should be enough to prove that there's no NULL-pointer dereference. Oh well. CID: 1405999 Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: rename tcs_tes_uses_prim_id for clarityNicolai Hähnle2017-05-163-9/+9
| | | | | | | | What we care about is whether PrimID is used while tessellation is enabled; whether it's used in TCS/TES or further down the pipeline is irrelevant. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: fix gl_PrimitiveIDIn in geometry shader when using tessellationNicolai Hähnle2017-05-161-0/+2
| | | | | | | | | | | This builds on commit 0549ea15ec38 ("radeonsi: fix primitive ID in fragment shader when using tessellation"). Fixes piglit arb_tessellation_shader/execution/gs-primitiveid-instanced.shader_test Cc: 17.1 <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: enable threaded_contextMarek Olšák2017-05-151-3/+34
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radeonsi: implement replace_buffer_storage for the threaded contextMarek Olšák2017-05-151-12/+22
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* gallium/radeon: unwrap a context if we get a wrapped oneMarek Olšák2017-05-151-1/+1
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radeonsi/gfx9: add support for RavenMarek Olšák2017-05-152-2/+8
| | | | | | Cc: 17.1 <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: get rid of secondary input/output wordNicolai Hähnle2017-05-123-47/+13
| | | | | | | By keeping track of fewer generics, everything can fit into 64 bits. Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: reduce the number of generics for shader IO unique indicesNicolai Hähnle2017-05-121-1/+1
| | | | | | | | | | | | This is a high as possible while still allowing to merge the bitfields with the next commit. For OpenGL, 32 would be sufficient. Nine apparently uses (much!) higher indices than. Indices that are out of bound don't hurt for VS-PS pipelines, except that the VS output kill optimization is not applied. Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: at most 8 sets of texture coordinates are supportedNicolai Hähnle2017-05-121-0/+1
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: skip generic out/in indices without a shader IO indexNicolai Hähnle2017-05-122-1/+9
| | | | | | | | | | | | | OpenGL uses at most 32 generic outputs/inputs in any stage, and they always have a shader IO index and therefore fit into the outputs_written/ inputs_read/kill_outputs fields. However, Nine uses semantic indices more liberally. We support that in VS-PS pipelines, except that the optimization of killing outputs must be skipped. Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: use SI_MAX_IO_GENERIC instead of magic valuesNicolai Hähnle2017-05-123-3/+8
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* Android: rework LLVM build supportRob Herring2017-05-111-0/+2
| | | | | | | | | | | | | Currently, building with "mmma external/mesa3d" which builds all targets and dependencies is broken for targets that require LLVM. This is due to the build settings depending on MESA_ENABLE_LLVM. Instead of using a conditional in the global Android.common.mk, make all the components that need LLVM explicitly include the necessary build settings. GALLIVM_CPP_SOURCES doesn't exist anymore, so remove that as well. Signed-off-by: Rob Herring <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* Android: push driver build details to driver makefilesRob Herring2017-05-111-1/+12
| | | | | | | | | | | | | src/gallium/targets/dri/Android.mk contains lots of conditional for individual drivers. Let's move these details into the individual driver makefiles. In the process, align the make driver conditionals with automake (i.e. HAVE_GALLIUM_*). Signed-off-by: Rob Herring <[email protected]> [Emil Velikov: add the radeon winsys for radeonsi] Signed-off-by: Emil Velikov <[email protected]>
* radeonsi: remove upload code for zero-stride vertex attribsMarek Olšák2017-05-101-26/+8
| | | | | | | st/mesa takes care of it now. Tested-by: Edmondo Tommasina <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* gallium: add PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEXMarek Olšák2017-05-101-0/+1
| | | | | | | The next patch will use it. This is really for svga and GL2-level drivers. Tested-by: Edmondo Tommasina <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* gallium: remove pipe_index_buffer and set_index_bufferMarek Olšák2017-05-103-65/+46
| | | | | | | | | | | | | | pipe_draw_info::indexed is replaced with index_size. index_size == 0 means non-indexed. Instead of pipe_index_buffer::offset, pipe_draw_info::start is used. For indexed indirect draws, pipe_draw_info::start is added to the indirect start. This is the only case when "start" affects indirect draws. pipe_draw_info::index is a union. Use either index::resource or index::user depending on the value of pipe_draw_info::has_user_indices. v2: fixes for nine, svga
* gallium: separate indirect stuff from pipe_draw_info - 80 -> 56 bytesMarek Olšák2017-05-101-27/+32
| | | | For faster initialization of non-indirect draws.
* gallium: decrease the size of pipe_vertex_buffer - 24 -> 16 bytesMarek Olšák2017-05-102-14/+14
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* radeonsi: silent a compiler warningSamuel Pitoiset2017-05-101-1/+1
| | | | | | | | | | | | | | This fixes: si_shader.c: In function ‘si_shader_dump_stats’: si_shader.c:6704:31: warning: passing argument 1 of ‘si_get_max_workgroup_size’ discards ‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers] si_get_max_workgroup_size(shader); ^~~~~~ si_shader.c:5832:17: note: expected ‘struct si_shader *’ but argument is of type ‘const struct si_shader *’ static unsigned si_get_max_workgroup_size(struct si_shader *shader) Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: dump compute descriptor listsNicolai Hähnle2017-05-101-0/+10
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: dump both enabled and required descriptor slotsNicolai Hähnle2017-05-101-6/+12
| | | | | | This allows a meaningful dump with info == NULL (for compute shaders). Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: dump compute shader as part of debug dumpNicolai Hähnle2017-05-101-0/+11
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: move struct si_compute into a headerNicolai Hähnle2017-05-103-21/+52
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: split descriptor list dumpingNicolai Hähnle2017-05-101-16/+21
| | | | | | Prepare for dumping CS descriptor list. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: split shader dumpingNicolai Hähnle2017-05-101-12/+18
| | | | | | Prepare for dumping compute shaders. Reviewed-by: Marek Olšák <[email protected]>
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