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* radeonsi/nir: fix input processing for packed varyingsTimothy Arceri2018-03-281-3/+2
| | | | | | | | | The location was only being incremented the first time we processed a location. This meant we would incorrectly skip some elements of an array if the first element was packed and proccessed previously but other elements were not. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/nir: fix scanning of multi-slot output varyingsTimothy Arceri2018-03-281-109/+127
| | | | | | | | | | This fixes tcs/tes varying arrays where we dont lower indirects and therefore don't split arrays. Here we also fix useagemask for dual slot doubles. Fixes a number of arb_tessellation_shader piglit tests. Reviewed-by: Marek Olšák <[email protected]>
* nir: Rename image intrinsics to image_varJason Ekstrand2018-03-231-9/+9
| | | | | | | | | | | Generated with git grep -l nir_intrinsic_image | xargs \ sed -i 's/nir_intrinsic_image/nir_intrinsic_image_var/g' and some manual fixing in nir_intrinsics.h Reviewed-by: Timothy Arceri <[email protected]>
* radeonsi: fix a snprintf warning on gcc 7.3.0Marek Olšák2018-03-211-1/+1
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* radeonsi/gfx9: print the swizzle mode for testdmaMarek Olšák2018-03-211-2/+16
| | | | Tested-by: Dieter Nützel <[email protected]>
* st/radeonsi: enable uniform packing in NIR backendTimothy Arceri2018-03-201-1/+5
| | | | Reviewed-by: Marek Olšák <[email protected]>
* gallium: add packed uniform CAPTimothy Arceri2018-03-201-0/+1
| | | | Reviewed-by: Marek Olšák <[email protected]>
* st/nir/radeonsi: move nir_lower_uniforms_to_ubo() to the state trackerTimothy Arceri2018-03-201-10/+0
| | | | | | | | | | | | | This will only ever be used by gallium drivers so it probably doesn't belong in the nir toolkit. Also we want to pass it some non NIR things in the following patch. To avoid regressions we wrap the lowering calls that have been moved to st_glsl_to_nir with a quick hack so that they are only called for radeonsi, we will replace the hack with a check for uniform packing in a following patch. Reviewed-by: Marek Olšák <[email protected]>
* ac/nir: pass the nir variable through tcs loading.Dave Airlie2018-03-141-5/+4
| | | | | | | | | | | | I was going to have to add another parameter to this monster, so we should just pass the nir_variable in, I can't find any reason this would be a bad idea. This needed for the next fix. Fixes: 94f9591995 (radv/ac: add support for TCS/TES inputs/outputs.) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* ac/nir: Use lower_vote_eq_to_ballot instead of ac_nir_lower_subgroupsJason Ekstrand2018-03-131-0/+1
| | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi: add a workaround for GFX9 hang with init_config alignmentMarek Olšák2018-03-091-1/+2
| | | | | Fixes: 75c5d25f0f34cd702 "radeonsi: align command buffer starting address to fix some Raven hangs" Cc: 17.3 18.0 <[email protected]>
* radeonsi: remove chip_class parameter from si_lower_nirMarek Olšák2018-03-084-10/+6
| | | | | | | We can get it from si_screen. Reviewed-by: Timothy Arceri <[email protected]> Acked-by: Alex Deucher <[email protected]>
* radeonsi: expand constbuf 0 address correctly to fix Vega10 hangsMarek Olšák2018-03-081-4/+17
| | | | | | | | | | This is only required with the latest libdrm. This fixes 32-bit support with high addresses. (and possibly 64-bit support too because the high bits need to be masked out) Acked-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]>
* radeonsi: align command buffer starting address to fix some Raven hangsMarek Olšák2018-03-081-2/+3
| | | | | | Cc: 17.3 18.0 <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* ac/radeonsi: add emit_kill to the abiTimothy Arceri2018-03-081-0/+1
| | | | | | | | This should fix a regression with Rocket League grass rendering on the NIR backend. Reviewed-by: Marek Olšák <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104717
* radeonsi: add si_llvm_emit_kill() helperTimothy Arceri2018-03-082-12/+21
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: make use of if/loop build helpers in acTimothy Arceri2018-03-082-160/+11
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: remove si_llvm_add_attributeMarek Olšák2018-03-073-25/+16
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* radeonsi: fix passing address32_hi to LLVM for high valuesMarek Olšák2018-03-071-2/+5
| | | | The old function treats high values as negative, which LLVM interprets as 0.
* radeonsi: add/update assertions for 32-bit address spaceMarek Olšák2018-03-071-1/+5
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* radeonsi: prevent a negative buffer offset in si_upload_descriptorsMarek Olšák2018-03-071-4/+3
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* radeonsi: properly extract a buffer address from a descriptorMarek Olšák2018-03-071-1/+7
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* radeonsi: fix vertex buffer address computation with full 64-bit addressesMarek Olšák2018-03-071-3/+3
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* radeonsi: mask out high VM address bits in registers where neededMarek Olšák2018-03-073-22/+24
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* ac: add ac_count_scratch_private_memory()Samuel Pitoiset2018-03-061-28/+4
| | | | | | | Imported from RadeonSI. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radeonsi/nir: fix handling of doubles for gs inputsTimothy Arceri2018-03-061-2/+6
| | | | | | | Fixes piglit test: tests/spec/arb_gpu_shader_fp64/execution/explicit-location-gs-fs-vs.shader_test Reviewed-by: Dave Airlie <[email protected]>
* radeonsi: move si_nir_load_input_gs() to si_shader.cTimothy Arceri2018-03-063-29/+20
| | | | | | | | All the tess shader and tgsi equivalents are here and it allows use to use llvm_type_is_64bit() in the following patch without exposing it externally. Reviewed-by: Dave Airlie <[email protected]>
* ac: add ac_build_fsign()Samuel Pitoiset2018-03-051-11/+4
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* ac: add ac_build_isign()Samuel Pitoiset2018-03-051-8/+2
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* ac: add ac_build_fract()Samuel Pitoiset2018-03-051-8/+5
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* radeonsi/nir: call ac_lower_indirect_derefs()Timothy Arceri2018-03-054-4/+6
| | | | | | | | Fixes piglit tests: tests/spec/glsl-1.50/execution/variable-indexing/gs-input-array-vec3-index-rd.shader_test tests/spec/glsl-1.50/execution/geometry/max-input-components.shader_test Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi: add chip class to compiler_ctx_stateTimothy Arceri2018-03-053-0/+4
| | | | | | This will be used in the following patch. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi: fix radeon create encoder returnBoyuan Zhang2018-03-021-1/+1
| | | | | | | | | | | Previous patch missed a "return" when trying to modify the create encoder function, which made the whole logic fail. Therefore, add the return back. Fixes: b38b208ff8886e799d6a2 "radeonsi:create uvd hevc enc entry" Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* radeonsi/nir: increase values to 8 for gs fetch.Dave Airlie2018-03-011-1/+1
| | | | | | | | This stops a crash when running (still fails): tests/spec/arb_gpu_shader_fp64/execution/explicit-location-gs-fs-vs.shader_test Reviewed-by: Timothy Arceri <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: set some context vars for nir pathTimothy Arceri2018-03-011-6/+10
| | | | Reviewed-by: Marek Olšák <[email protected]>
* ac/radeonsi: add load_base_vertex() to the abiTimothy Arceri2018-02-281-0/+1
| | | | | | | | | | Fixes the following piglit tests: ./bin/arb_shader_draw_parameters-basevertex basevertex -auto -fbo ./bin/arb_shader_draw_parameters-basevertex basevertex-baseinstance -auto -fbo Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: create get_base_vertex() helperTimothy Arceri2018-02-281-14/+20
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/nir: disable vertex_id_zero_based loweringTimothy Arceri2018-02-281-1/+0
| | | | | | | | | | The lowering is incompatible with how the radeonsi backend works. Fixes piglit test: ./bin/arb_shader_draw_parameters-basevertex vertexid-zerobased -auto Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: remove 2 unused user SGPRs from merged TES-GS with 32-bit pointersMarek Olšák2018-02-264-11/+35
| | | | | | The effect of the last 13 commits on user SGPR counts: Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: make SI_SGPR_VERTEX_BUFFERS the last user SGPR inputMarek Olšák2018-02-264-20/+53
| | | | | | | | so that it can be removed and replaced with inline VBO descriptors, and the pointer can be packed in unused bits of VBO descriptors. This also removes the pointer from merged TES-GS where it's useless. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: set correct num_input_sgprs for VS prolog in merged shadersMarek Olšák2018-02-261-24/+24
| | | | | | | We need to take num_input_sgprs from VS, not the second shader. No apps suffered from this. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: allow fewer input SGPRs in 2nd shader of merged shadersMarek Olšák2018-02-261-1/+5
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: don't use struct si_descriptors for vertex buffer descriptorsMarek Olšák2018-02-266-33/+46
| | | | | | VBO descriptor code will change a lot one day. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/nir: enable lowering of fpowTimothy Arceri2018-02-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Lowering fpow in NIR rather than LLVM can be beneficial. Polaris results: Totals from affected shaders: SGPRS: 124928 -> 124896 (-0.03 %) VGPRS: 68616 -> 68332 (-0.41 %) Spilled SGPRs: 394 -> 413 (4.82 %) Spilled VGPRs: 0 -> 0 (0.00 %) Private memory VGPRs: 0 -> 0 (0.00 %) Scratch size: 0 -> 0 (0.00 %) dwords per thread Code Size: 3668912 -> 3658368 (-0.29 %) bytes LDS: 0 -> 0 (0.00 %) blocks Max Waves: 18575 -> 18593 (0.10 %) Wait states: 0 -> 0 (0.00 %) Fixes: d6b753920677 "ac/nir: remove emission of nir_op_fpow" Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/nir: fix loading of doubles for tess varyingsTimothy Arceri2018-02-261-2/+10
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/nir: fix lds store in tcs outputs handlingTimothy Arceri2018-02-261-1/+1
| | | | | | We were ignoring the channel offset. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: remove si_descriptors parameter from emit_shader_pointer functionsMarek Olšák2018-02-241-12/+13
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: preload the tess offchip ring in TESMarek Olšák2018-02-242-12/+10
| | | | | | so that it's not done multiple times in branches Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move tess ring address into TCS_OUT_LAYOUT, removes 2 TCS user SGPRsMarek Olšák2018-02-245-91/+70
| | | | | | | TCS_OUT_LAYOUT has 13 unused bits. That's enough for a 32-bit address aligned to 512KB. Hey, it's a 13-bit pointer! Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move 2nd-shader descriptor pointers into s[0:1]Marek Olšák2018-02-243-74/+140
| | | | | | | | | | | If 32-bit pointers are supported, both pointers can be moved into s[0:1] and then ESGS has exactly the same user data SGPR declarations as VS. If 32-bit pointers are not supported, only one pointer can be moved into s[0:1]. In that case, the 2nd pointer is moved before TCS constants, so that the location is the same in HS and GS. Reviewed-by: Nicolai Hähnle <[email protected]>
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