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* radeonsi: Only honour point related rasterizer state when rendering points.Michel Dänzer2012-05-181-2/+3
| | | | Avoids hangs when not rendering points.
* radeonsi: Fix parameter cache offsets for fragment shader inputs.Michel Dänzer2012-05-183-2/+4
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* gallium/radeon: Fix r300g tiling breakage.Michel Dänzer2012-05-161-0/+1
| | | | | | Commit 11f056a3f0b87e86267efa8b5ac9d36a343c9dc1 broke the r300g build. Fix it up, and reinstate some code which isn't needed by r600g and radeonsi but is by r300g.
* radeonsi: Initial tiling support.Michel Dänzer2012-05-165-128/+356
| | | | Largely based on the corresponding Evergreen support in r600g.
* radeonsi: Bump MAX_DRAW_CS_DWORDS.Michel Dänzer2012-05-163-3/+3
| | | | I missed this when updating si_context_draw().
* radeonsi: Keep around copies of original sampler states.Michel Dänzer2012-05-141-0/+2
| | | | Fixes crashes when restoring sampler states after blits.
* radeonsi: Flesh out shader interpolation related code.Michel Dänzer2012-05-141-4/+17
| | | | Handle perspective interpolation and ceontroid vs. center.
* radeonsi: Add proper SI family names.Michel Dänzer2012-05-141-1/+3
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* radeonsi: Separate states for samplers and sampler views.Michel Dänzer2012-05-142-3/+6
| | | | And reset nregs on updates. Prevents eventual assertion failure.
* radeonsi: Fixups for drawing with an index buffer.Michel Dänzer2012-05-143-14/+13
| | | | | Mostly using the DRAW_INDEX_2 type 3 packet instead of DRAW_INDEX, which is no longer supported on SI.
* radeonsi: remove slab allocator for pipe_resource (used mainly for user buffers)Marek Olšák2012-05-133-41/+3
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* gallium: remove user_buffer_create from the interfaceMarek Olšák2012-05-123-29/+0
| | | | Nothing uses it now.
* radeonsi: Fixed point vertex formats aren't supported.Michel Dänzer2012-05-121-4/+5
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* Merge branch 'gallium-userbuf'Marek Olšák2012-05-117-43/+38
|\ | | | | | | | | | | | | | | Conflicts: src/gallium/docs/source/screen.rst src/gallium/drivers/nv50/nv50_state.c src/gallium/include/pipe/p_defines.h src/mesa/state_tracker/st_draw.c
| * gallium: remove pipe_resource::user_ptrMarek Olšák2012-04-301-5/+0
| | | | | | | | It's unused now.
| * radeonsi: don't create temporary user buffer for r600_upload_const_bufferMarek Olšák2012-04-303-32/+25
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| * gallium: add void *user_buffer to pipe_constant_bufferMarek Olšák2012-04-301-0/+6
| | | | | | | | This reduces CPU overhead when updating constants.
| * gallium: add void *user_buffer in pipe_index_bufferMarek Olšák2012-04-303-6/+3
| | | | | | | | | | | | | | Adapted drivers: i915, llvmpipe, r300, r600, radeonsi, softpipe. User index buffers have been disabled in nv30, nv50, nvc0 and svga to keep things working.
| * gallium: remove pipe_context::redefine_user_bufferMarek Olšák2012-04-301-1/+0
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| * gallium: change set_constant_buffer to be UBO-friendlyMarek Olšák2012-04-302-5/+5
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| * gallium: add PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENTMarek Olšák2012-04-301-0/+3
| | | | | | | | | | | | | | | | This is required for any serious constant buffer support. Constant buffer offsets on ATI and NVIDIA DX10 and DX11 GPUs must be a multiple of 256. In OpenGL, this can be queried via GL_UNIFORM_BUFFER_OFFSET_ALIGNMENT.
| * gallium: add PIPE_CAP_USER_INDEX_BUFFERS and PIPE_CAP_USER_CONSTANT_BUFFERSMarek Olšák2012-04-301-0/+2
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* | gallium/tgsi: Move interpolation info from tgsi_declaration to a separate token.Francisco Jerez2012-05-111-4/+4
| | | | | | | | | | | | Move Interpolate, Centroid and CylindricalWrap from tgsi_declaration to a separate token -- they only make sense for FS inputs and we need room for other flags in the top-level declaration token.
* | radeonsi: Properly translate vertex format swizzle.Michel Dänzer2012-05-113-23/+23
| | | | | | | | egltri_screen works correctly!
* | radeonsi: Set NONE format for unused vertex shader position export slots.Michel Dänzer2012-05-101-3/+3
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* | radeonsi: Eliminate one more magic number for texture image resources.Michel Dänzer2012-05-101-3/+3
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* | radeonsi: Fix vertex buffer resource for stride 0.Michel Dänzer2012-05-101-1/+5
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* radeonsi: make r600_buffer_transfer_unmap a no-opMarek Olšák2012-04-291-7/+1
| | | | It's a no-op already in the winsys.
* radeonsi: use u_default_transfer_inline_writeMarek Olšák2012-04-293-26/+3
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* winsys/radeon: simplify buffer map/unmap functionsMarek Olšák2012-04-297-35/+35
| | | | | The idea is not to use pb_map and pb_unmap wrappers, calling straight into the winsys.
* radeonsi: stop using u_vbuf and adapt to gallium interface changesMarek Olšák2012-04-2411-98/+100
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* gallium: add user_ptr in pipe_resourceMarek Olšák2012-04-241-0/+1
| | | | I need to access the pointer in st/mesa when I only have pipe_resource.
* radeon: Move radeon_llvm_emit.cpp declarations into their own headerTom Stellard2012-04-231-0/+1
| | | | Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: Replace magic numbers for vertex buffer resource.Michel Dänzer2012-04-191-4/+8
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* radeonsi: (User) SGPR related cleanups.Michel Dänzer2012-04-193-16/+33
| | | | | | Use the same user SGPRs for the same purpose in vertex and pixel shaders. Better calculation of the number of SGPRs to reserve.
* radeonsi: Fix sampler offsets for shader intrinsic.Michel Dänzer2012-04-191-2/+2
| | | | | The sampler number is in TGSI source register 1, and the S_LOAD_DWORD* instructions take offsets in DWORDs, not bytes.
* radeonsi: Replace more magic numbers for sampler state.Michel Dänzer2012-04-191-7/+7
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* radeonsi: Fix mip filter encoding in sampler state.Michel Dänzer2012-04-191-3/+3
| | | | Blits are starting to work.
* radeonsi: Set tiling mode index for depth/stencil buffers.Michel Dänzer2012-04-191-19/+37
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* radeonsi: Improve calculation of number of pixel shader interpolants.Michel Dänzer2012-04-181-23/+7
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* radeonsi: Fix calculation of pitch value in sampler view state.Michel Dänzer2012-04-181-4/+2
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* radeonsi: Set tiling mode index in sampler view state.Michel Dänzer2012-04-181-0/+1
| | | | Hardcode index for linear mode for now.
* radeonsi: Replace magic numbers with register definitions in sampler state.Michel Dänzer2012-04-181-15/+15
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* radeonsi: Fix white border color type in sampler state.Michel Dänzer2012-04-181-1/+1
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* radeonsi: s/DUAL_SOURCE_BLEND/MAX_DUAL_SOURCE_RENDER_TARGETS/Tom Stellard2012-04-141-1/+1
| | | | Fixes build broken by commit 0d29fb017bce0968240ae875af4b3702c2cd46ef
* radeonsi: initial WIP SI codeTom Stellard2012-04-1323-0/+16520
This commit adds initial support for acceleration on SI chips. egltri is starting to work. The SI/R600 llvm backend is currently included in mesa but that may change in the future. The plan is to write a single gallium driver and use gallium to support X acceleration. This commit contains patches from: Tom Stellard <[email protected]> Michel Dänzer <[email protected]> Alex Deucher <[email protected]> Vadim Girlin <[email protected]> Signed-off-by: Alex Deucher <[email protected]> The following commits were squashed in: ====================================================================== radeonsi: Remove unused winsys pointer This was removed from r600g in commit: commit 96d882939d612fcc8332f107befec470ed4359de Author: Marek Olšák <[email protected]> Date: Fri Feb 17 01:49:49 2012 +0100 gallium: remove unused winsys pointers in pipe_screen and pipe_context A winsys is already a private object of a driver. ====================================================================== radeonsi: Copy color clamping CAPs from r600 Not sure if the values of these CAPS are correct for radeonsi, but the same changed were made to r600g in commit: commit bc1c8369384b5e16547c5bf9728aa78f8dfd66cc Author: Marek Olšák <[email protected]> Date: Mon Jan 23 03:11:17 2012 +0100 st/mesa: do vertex and fragment color clamping in shaders For ARB_color_buffer_float. Most hardware can't do it and st/mesa is the perfect place for a fallback. The exceptions are: - r500 (vertex clamp only) - nv50 (both) - nvc0 (both) - softpipe (both) We also have to take into account that r300 can do CLAMPED vertex colors only, while r600 can do UNCLAMPED vertex colors only. The difference can be expressed with the two new CAPs. ====================================================================== radeonsi: Remove PIPE_CAP_OUTPUT_READ This CAP was dropped in commit: commit 04e324008759282728a95a1394bac2c4c2a1a3f9 Author: Marek Olšák <[email protected]> Date: Thu Feb 23 23:44:36 2012 +0100 gallium: remove PIPE_SHADER_CAP_OUTPUT_READ r600g is the only driver which has made use of it. The reason the CAP was added was to fix some piglit tests when the GLSL pass lower_output_reads didn't exist. However, not removing output reads breaks the fallback for glClampColorARB, which assumes outputs are not readable. The fix would be non-trivial and my personal preference is to remove the CAP, considering that reading outputs is uncommon and that we can now use lower_output_reads to fix the issue that the CAP was supposed to workaround in the first place. ====================================================================== radeonsi: Add missing parameters to rws->buffer_get_tiling() call This was changed in commit: commit c0c979eebc076b95cc8d18a013ce2968fe6311ad Author: Jerome Glisse <[email protected]> Date: Mon Jan 30 17:22:13 2012 -0500 r600g: add support for common surface allocator for tiling v13 Tiled surface have all kind of alignment constraint that needs to be met. Instead of having all this code duplicated btw ddx and mesa use common code in libdrm_radeon this also ensure that both ddx and mesa compute those alignment in the same way. v2 fix evergreen v3 fix compressed texture and workaround cube texture issue by disabling 2D array mode for cubemap (need to check if r7xx and newer are also affected by the issue) v4 fix texture array v5 fix evergreen and newer, split surface values computation from mipmap tree generation so that we can get them directly from the ddx v6 final fix to evergreen tile split value v7 fix mipmap offset to avoid to use random value, use color view depth view to address different layer as hardware is doing some magic rotation depending on the layer v8 fix COLOR_VIEW on r6xx for linear array mode, use COLOR_VIEW on evergreen, align bytes per pixel to a multiple of a dword v9 fix handling of stencil on evergreen, half fix for compressed texture v10 fix evergreen compressed texture proper support for stencil tile split. Fix stencil issue when array mode was clear by the kernel, always program stencil bo. On evergreen depth buffer bo need to be big enough to hold depth buffer + stencil buffer as even with stencil disabled things get written there. v11 rebase on top of mesa, fix pitch issue with 1d surface on evergreen, old ddx overestimate those. Fix linear case when pitch*height < 64. Fix r300g. v12 Fix linear case when pitch*height < 64 for old path, adapt to libdrm API change v13 add libdrm check Signed-off-by: Jerome Glisse <[email protected]> ====================================================================== radeonsi: Remove PIPE_TRANSFER_MAP_PERMANENTLY This was removed in commit: commit 62f44f670bb0162e89fd4786af877f8da9ff607c Author: Marek Olšák <[email protected]> Date: Mon Mar 5 13:45:00 2012 +0100 Revert "gallium: add flag PIPE_TRANSFER_MAP_PERMANENTLY" This reverts commit 0950086376b1c8b7fb89eda81ed7f2f06dee58bc. It was decided to refactor the transfer API instead of adding workarounds to address the performance issues. ====================================================================== radeonsi: Handle PIPE_VIDEO_CAP_PREFERED_FORMAT. Reintroduced in commit 9d9afcb5bac2931d4b8e6d1aa571e941c5110c90. ====================================================================== radeonsi: nuke the fallback for vertex and fragment color clamping Ported from r600g commit c2b800cf38b299c1ab1c53dc0e4ea00c7acef853. ====================================================================== radeonsi: don't expose transform_feedback2 without kernel support Ported from r600g commit 15146fd1bcbb08e44a1cbb984440ee1a5de63d48. ====================================================================== radeonsi: Handle PIPE_CAP_GLSL_FEATURE_LEVEL. Ported from r600g part of commit 171be755223d99f8cc5cc1bdaf8bd7b4caa04b4f. ====================================================================== radeonsi: set minimum point size to 1.0 for non-sprite non-aa points. Ported from r600g commit f183cc9ce3ad1d043bdf8b38fd519e8f437714fc. ====================================================================== radeonsi: rework and consolidate stencilref state setting. Ported from r600g commit a2361946e782b57f0c63587841ca41c0ea707070. ====================================================================== radeonsi: cleanup setting DB_SHADER_CONTROL. Ported from r600g commit 3d061caaed13b646ff40754f8ebe73f3d4983c5b. ====================================================================== radeonsi: Get rid of register masks. Ported from r600g commits 3d061caaed13b646ff40754f8ebe73f3d4983c5b..9344ab382a1765c1a7c2560e771485edf4954fe2. ====================================================================== radeonsi: get rid of r600_context_reg. Ported from r600g commits 9344ab382a1765c1a7c2560e771485edf4954fe2..bed20f02a771f43e1c5092254705701c228cfa7f. ====================================================================== radeonsi: Fix regression from 'Get rid of register masks'. ====================================================================== radeonsi: optimize r600_resource_va. Ported from r600g commit 669d8766ff3403938794eb80d7769347b6e52174. ====================================================================== radeonsi: remove u8,u16,u32,u64 types. Ported from r600g commit 78293b99b23268e6698f1267aaf40647c17d95a5. ====================================================================== radeonsi: merge r600_context with r600_pipe_context. Ported from r600g commit e4340c1908a6a3b09e1a15d5195f6da7d00494d0. ====================================================================== radeonsi: Miscellaneous context cleanups. Ported from r600g commits e4340c1908a6a3b09e1a15d5195f6da7d00494d0..621e0db71c5ddcb379171064a4f720c9cf01e888. ====================================================================== radeonsi: add a new simple API for state emission. Ported from r600g commits 621e0db71c5ddcb379171064a4f720c9cf01e888..f661405637bba32c2cfbeecf6e2e56e414e9521e. ====================================================================== radeonsi: Also remove sbu_flags member of struct r600_reg. Requires using sid.h instead of r600d.h for the new CP_COHER_CNTL definitions, so some code needs to be disabled for now. ====================================================================== radeonsi: Miscellaneous simplifications. Ported from r600g commits 38bf2763482b4f1b6d95cd51aecec75601d8b90f and b0337b679ad4c2feae59215104cfa60b58a619d5. ====================================================================== radeonsi: Handle PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION. Ported from commit 8b4f7b0672d663273310fffa9490ad996f5b914a. ====================================================================== radeonsi: Use a fake reloc to sleep for fences. Ported from r600g commit 8cd03b933cf868ff867e2db4a0937005a02fd0e4. ====================================================================== radeonsi: adapt to get_query_result interface change. Ported from r600g commit 4445e170bee23a3607ece0e010adef7058ac6a11.
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