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* radeonsi/compute: Fix memory leakAaron Watry2014-03-151-0/+6
| | | | | | Free shader buffer object for all kernels when deleting compute state. Signed-off-by: Aaron Watry <[email protected]>
* radeonsi: flush the dma ring in si_flush_from_stNiels Ole Salscheider2014-03-141-0/+7
| | | | | Signed-off-by: Niels Ole Salscheider <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* r600g,radeonsi: attempt to fix racy multi-context apps calling BufferDataMarek Olšák2014-03-111-4/+1
| | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75061 v2: minimize the window where cs_buf != new_buf
* r600g,radeonsi: use a fallback in dma_copy instead of failingMarek Olšák2014-03-111-8/+11
| | | | | | v2: - allow byte-aligned DMA buffer copies on Evergreen - fix piglit/texsubimage regression - use the fallback for 3D copies (depth > 1) as well
* radeonsi: small cleanup in get_paramMarek Olšák2014-03-111-4/+2
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: set correct alignment for texture buffers and constant buffersMarek Olšák2014-03-111-3/+2
| | | | | | | I think these are all equivalent to vertex buffer fetches which should be dword-aligned. Scalar loads are also dword-aligned. Reviewed-by: Michel Dänzer <[email protected]>
* r600g, radeonsi: fix primitives-generated query with disabled streamoutMarek Olšák2014-03-114-1/+3
| | | | | | | | | | | | | | | | | Buffers are disabled by VGT_STRMOUT_BUFFER_CONFIG, but the query only works if VGT_STRMOUT_CONFIG.STREAMOUT_0_EN is enabled. This moves VGT_STRMOUT_CONFIG to its own state. The register is set to 1 if either streamout or the primitives-generated query is enabled. However, the primitives-emitted query is also incremented, so it's disabled by setting VGT_STRMOUT_BUFFER_SIZE to 0 when there is no buffer bound. This fixes piglit: ARB_transform_feedback2/counting with pause EXT_transform_feedback/primgen-query transform-feedback-disabled Reviewed-by: Michel Dänzer <[email protected]>
* r600g,radeonsi: fix MAX_TEXTURE_3D_LEVELS and MAX_TEXTURE_ARRAY_LAYERS limitsMarek Olšák2014-03-111-3/+6
| | | | | | | | | CB_COLORi_VIEW.SLICE_MAX can be at most 2047. This fixes the maxlayers piglit test. Cc: [email protected] Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: implement fast color clearMarek Olšák2014-03-114-3/+54
| | | | | | This works for both multi-sample and single-sample color buffers. Reviewed-by: Michel Dänzer <[email protected]>
* r600g,radeonsi: move CMASK register values from r600_surface to r600_textureMarek Olšák2014-03-111-15/+7
| | | | | | | | | | | When doing fast clear for single-sample color buffers for the first time, a CMASK buffer has to be allocated and the CMASK state in all pipe_surfaces referencing the color buffer must be updated. Updating all surfaces is kinda silly, so let's move the values to r600_texture instead. This is only for Evergreen and later. R600-R700 don't have fast clear. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: convert the framebuffer state to atom-basedMarek Olšák2014-03-115-283/+132
| | | | | | | | | | | This looks like r600g. The shared Cayman MSAA code is used here. The real motivation for this is that I need the ability to change values of color registers after the framebuffer state is set. The PM4 state cannot be modified easily after it's generated. With this, I can just change r600_surface::cb_color_xxx and set framebuffer.atom.dirty=true and it's done. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: move framebuffer-related state to a new struct si_framebufferMarek Olšák2014-03-115-39/+41
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* r600g,radeonsi: set priorities for relocationsMarek Olšák2014-03-117-35/+76
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* gallium: allow setting of the internal stream output offsetZack Rusin2014-03-071-2/+2
| | | | | | | | | | | | | | | | D3D10 allows setting of the internal offset of a buffer, which is in general only incremented via actual stream output writes. By allowing setting of the internal offset draw_auto is capable of rendering from buffers which have not been actually streamed out to. Our interface didn't allow. This change functionally shouldn't make any difference to OpenGL where instead of an append_bitmask you just get a real array where -1 means append (like in D3D) and 0 means do not append. Signed-off-by: Zack Rusin <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Use proper member name for deleting export shader PM4 stateMichel Dänzer2014-03-101-0/+2
| | | | | | Fixes double-free with some piglit tests using geometry shaders. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: fix freeing descriptor buffersChristian König2014-03-081-1/+1
| | | | | | | | That structure member is a pointer, so the loop with the Elements macro only freed up the first entry. Signed-off-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: fix leaking the bound state on destruction v2Christian König2014-03-083-0/+10
| | | | | | | v2: rebased on stale pointer fixes Signed-off-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: avoid stale state pointersChristian König2014-03-081-9/+3
| | | | | Signed-off-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: avoid stale pointers in si_delete_shader_selectorChristian König2014-03-081-1/+6
| | | | | Signed-off-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeon: Rename struct radeon_llvm_binary to radeon_shader_binary v2Tom Stellard2014-03-071-1/+1
| | | | | | | | | | And move its definition into r600_pipe_common.h; This struct is a just a container for shader code and has nothing to do with LLVM. v2: - Drop unrelated Makefile change Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: fix blit compressed texture workaround to support 2D arraysMarek Olšák2014-03-071-1/+2
| | | | | | We don't have a piglit test for this, but I think it's correct. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: move translate_colorswap to common codeMarek Olšák2014-03-041-54/+2
| | | | | | | Also translate the Y__X swizzle. Cc: [email protected] Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: Prevent geometry shader from emitting too many verticesMichel Daenzer2014-02-271-0/+16
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* r600g,radeonsi: consolidate create_surface and surface_destroyMarek Olšák2014-02-252-38/+4
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: inline util_blitter_copy_textureMarek Olšák2014-02-251-3/+21
| | | | | | | | This will be used for changing texture properties without modifying pipe_resource like r600g, but not in this series. For now, this change allows consolidation of pipe_surface functions. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: remove useless psbox variable from resource_copy_regionMarek Olšák2014-02-251-3/+2
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: compute depth surface registers only onceMarek Olšák2014-02-251-44/+54
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: compute color surface registers only onceMarek Olšák2014-02-251-44/+55
| | | | | | Same as r600g. Reviewed-by: Michel Dänzer <[email protected]>
* r600g,radeonsi: share r600_surfaceMarek Olšák2014-02-253-10/+5
| | | | | | I'm gonna use this in radeonsi. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: move PA_SU_POLY_OFFSET_DB_FMT_CNTL to framebuffer stateMarek Olšák2014-02-251-8/+21
| | | | | | It doesn't depend on anything else. Reviewed-by: Michel Dänzer <[email protected]>
* r300g,r600g,radeonsi: add support for ARB_buffer_storageMarek Olšák2014-02-251-0/+1
| | | | | | All GTT memory mappings are coherent and therefore can be persistent. Reviewed-by: Fredrik Höglund <[email protected]>
* gallium: add texture gather support to gallium (v3)Dave Airlie2014-02-251-0/+2
| | | | | | | | | | | | | | | | | | | | | This adds support to gallium for a TG4 instruction, and two CAPs. The first CAP is required for GL_ARB_texture_gather. The second CAP is required to expose GL_ARB_gpu_shader5. However so far we haven't found any hardware that natively exposes the textureGatherOffsets feature from GL, so just lower it for now. If hardware appears for this we can add another CAP to allow TG4 to take 4 offsets. v2: add component selection src and a cap to say hw can do it. (st can use to help control GL_ARB_gpu_shader5/GLSL 4.00). Add docs. v3: rename to SM5, add docs. Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* clover: Pass buffer offsets to the driver in set_global_binding() v3Tom Stellard2014-02-241-0/+4
| | | | | | | | | | | | | | | The offsets will be stored in the handles parameter. This makes it possible to use sub-buffers. v2: - Style fixes - Add support for constant sub-buffers - Store handles in device byte order v3: - Use endian helpers Reviewed-by: Francisco Jerez <[email protected]>
* radeonsi: Use SI_BIG_ENDIAN now that it existsTom Stellard2014-02-241-1/+1
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: Use util_cpu_to_le32() instead of bswap32() on big-endian systemsTom Stellard2014-02-242-2/+2
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* r600g,radeonsi: Consolidate logic for short-circuiting flushesMichel Dänzer2014-02-181-1/+3
| | | | | | | | | | | | | | | Fixes radeonsi emitting command streams to the kernel even when there have been no draw calls before a flush, potentially powering up the GPU needlessly. Incidentally, this also cuts the runtime of piglit gpu.py in about half on my Kaveri system, probably because an X11 client going away no longer always results in a command stream being submitted to the kernel via glamor. Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=65761 Cc: "10.1" [email protected] Reviewed-by: Marek Olšák <[email protected]>
* radeon/vce: initial VCE support v8Christian König2014-02-131-0/+20
| | | | | | | | | | | | | | v2 (chk): revert feedback buffer hack v3 (slava): fixed bitstream size calculation v4 (chk): always create buffers in the right domain v5 (chk): flush async v6 (chk): rework fw interface add version check v7 (leo): implement cropping support v8 (chk): add hw checks Signed-off-by: Christian König <[email protected]> Signed-off-by: Leo Liu <[email protected]> Signed-off-by: Slava Grigorev <[email protected]>
* gallium: add geometry shader output limitsGrigori Goronzy2014-02-091-0/+6
| | | | | | | | v2: adjust limits for radeonsi and llvmpipe v3: add documentation Cc: "10.1" <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* gallium: remove PIPE_USAGE_STATICMarek Olšák2014-02-064-7/+7
| | | | Reviewed-by: Brian Paul <[email protected]>
* r600g,radeonsi: set resource domains in one place (v2)Marek Olšák2014-02-061-2/+2
| | | | | | | v2: This doesn't change the behavior. It only moves the tiling check to r600_init_resource and removes the usage parameter. Reviewed-by: Christian König <[email protected]>
* radeon/video: seperate common video functionsChristian König2014-02-061-1/+2
| | | | Signed-off-by: Christian König <[email protected]>
* gallium: remove PIPE_CAP_MAX_COMBINED_SAMPLERSMarek Olšák2014-02-041-2/+0
| | | | | | | This can be derived from the shader caps. All GPUs from ATI/AMD, NVIDIA, and INTEL have separate texture slots for each shader stage.
* radeonsi: Put GS ring buffer descriptors with streamout buffer descriptorsMichel Dänzer2014-01-295-84/+115
| | | | | | And mark the constant buffers as read only for the GPU again. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Enable OpenGL 3.3Michel Dänzer2014-01-291-3/+5
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Geometry shader micro-optimizationsMichel Dänzer2014-01-291-12/+10
| | | | | | | | Move parameter loads out of loops, and use the instruction offset instead of a VGPR for the vertex attribute offset when writing to the ESGS ring buffer. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: We don't support indirect addressing of geometry shader inputsMichel Dänzer2014-01-291-0/+4
| | | | | | Fixes piglit spec/glsl-1.50/execution/geometry/dynamic_input_array_index Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Pass VS resource descriptors to the HW ES shader stage as wellMichel Dänzer2014-01-296-34/+58
| | | | | | | This makes sure constants and samplers work in the vertex shader even when a geometry shader is active. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Fix streamout from geometry shaderMichel Dänzer2014-01-291-10/+27
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Simplify shader PM4 state handlingMichel Dänzer2014-01-293-61/+21
| | | | | | | | | | Just always bind the current states before drawing. Besides the simplification, as a bonus this makes sure the VS hardware shader stage always uses the GS copy shader when a geometry shader is active, fixing a number of GS related piglit tests. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Properly match ES outputs to GS inputsMichel Dänzer2014-01-291-5/+16
| | | | | | Fixes piglit vs-gs-arrays-within-blocks-pass. Reviewed-by: Marek Olšák <[email protected]>
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