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* gallium/radeonsi: ship all files in the tarballEmil Velikov2014-09-052-0/+8
| | | | | | | | - include all headers in Makefile.sources - bundle the android buildscript Signed-off-by: Emil Velikov <[email protected]> Acked-by: Matt Turner <[email protected]>
* radeonsi: Compile dummy pixel shader on demandMichel Dänzer2014-09-022-8/+10
| | | | | | It's never used under normal circumstances. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: implement EXPCLEAR optimization for depthMarek Olšák2014-09-014-2/+22
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: implement fast depth clearMarek Olšák2014-09-014-2/+21
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: move DB_RENDER_CONTROL into draw_vboMarek Olšák2014-09-015-58/+46
| | | | | | So that I can add fast depth clear. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: disable occlusion queries if they are not neededMarek Olšák2014-09-011-0/+8
| | | | | | | We always left them enabled, which turned off HiZ in some cases. This should improve performace with Hyper-Z. Reviewed-by: Michel Dänzer <[email protected]>
* r600g,radeonsi: force fast stencil and HTILE stencil off, fixing a Hyper-Z hangMarek Olšák2014-09-011-8/+10
| | | | | | | | | | | | | This should be as fast as no HTILE for stencil. I think we can still get full performance with depth-only rendering even if stencil is present in the buffer but not used, but I'm not 100% sure. This may be revisited when HiS and fast stencil clear are implemented. This fixes a hang in Brutal Legend. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=64471 Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: set DB_DEPTH_SIZE.HEIGHT_TILE_MAX, inline other fieldsMarek Olšák2014-09-011-9/+8
| | | | | | | | | | This fixes rendering to a non-zero layer/face/slice with HTILE. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=72685 v2: added the assertion Reviewed-by: Michel Dänzer <[email protected]>
* gallium/radeon: cleanup header inclusionEmil Velikov2014-08-2810-12/+11
| | | | | | | | | | | | | | - Add top_srcdir/src/gallium/winsys to GALLIUM_DRIVER_C{XXFLAGS}. - Remove top_srcdir/src/gallium/drivers/radeon from the includes. As a result: - Common radeon headers are prefixed with 'radeon/' - Winsys header inclusion is prefixed 'radeon/drm' Cc: Marek Olšák <[email protected]> Cc: Michel Dänzer <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium: add cap for MAX_VERTEX_ATTRIB_STRIDETimothy Arceri2014-08-271-0/+3
| | | | | Signed-off-by: Timothy Arceri <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* radeonsi: handle PIPE_BIND_BLENDABLEMarek Olšák2014-08-251-1/+5
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* gallium: Add and handle PIPE_CAP_CONDITIONAL_RENDER_INVERTEDTobias Klausmann2014-08-191-0/+1
| | | | | | Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Tobias Klausmann <[email protected]>
* radeonsi: bump PRIMGROUP_SIZE for some casesMarek Olšák2014-08-191-1/+4
| | | | | | | Recommended by hw people. Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: set PARTIAL_VS_WAVE(0) when appropriateMarek Olšák2014-08-191-1/+6
| | | | | Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: set IA_MULTI_VGT_PARAM on SI the same as on CIK (v2)Marek Olšák2014-08-192-46/+50
| | | | | | | Nothing's changed for CIK here. Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: simplify si_num_banks functionMarek Olšák2014-08-193-15/+13
| | | | | | This makes it easier to use. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: use r600_draw_rectangle from r600gMarek Olšák2014-08-193-5/+5
| | | | | | Rectangles are easier than triangles for the rasterizer. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: save scissor state and sample mask for u_blitterMarek Olšák2014-08-193-8/+29
| | | | | Cc: [email protected] Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: don't set CB_SHADER_MASK=1 if there are no color outputsMarek Olšák2014-08-191-4/+0
| | | | | | This hack isn't needed anymore because of the previous u_blitter commit. Reviewed-by: Michel Dänzer <[email protected]>
* gallium/r300/r600/radeonsi: handle query_renderer capsEmil Velikov2014-08-151-0/+11
| | | | | Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium: add opcodes/cap for fine derivative supportIlia Mirkin2014-08-141-0/+1
| | | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]> (v1) Reviewed-by: Roland Scheidegger <[email protected]> (v1) v2: Reuse opcode gaps as suggested by Marek
* radeonsi: implement BPTC texture supportGrigori Goronzy2014-08-141-0/+20
| | | | | | | | Passes all piglit tests. v2: rebased Signed-off-by: Marek Olšák <[email protected]>
* radeonsi: fix buffer invalidation of unbound texture buffer objectsMarek Olšák2014-08-143-7/+17
| | | | | | | This maintains a list of all TBOs in a pipe_context. Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi/compute: Stop leaking the input bufferTom Stellard2014-08-131-7/+14
| | | | | | | | We were leaking the input buffer used for kernel arguments and since we were allocating it using si_upload_const_buffer() we were leaking 1 MB per kernel invocation. CC: "10.2" <[email protected]>
* radeonsi/compute: Whitespace fixesTom Stellard2014-08-131-2/+1
| | | | CC: "10.2" <[email protected]>
* radeonsi/compute: Call si_pm4_free_state() after emitting compute stateTom Stellard2014-08-131-1/+1
| | | | | | | This will decrement the reference count for buffers referenced in the command stream will prevent us from leaking them. CC: "10.2" <[email protected]>
* radeonsi/compute: Update reference counts for buffers in si_set_global_binding()Tom Stellard2014-08-131-2/+2
| | | | CC: "10.2" <[email protected]>
* radeon/compute: Report a value for PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZETom Stellard2014-08-131-0/+7
| | | | CC: "10.2" <[email protected]>
* android: gallium/radeon: attempt to fix the android buildPaulo Sergio Travaglia2014-08-131-1/+1
| | | | | | | | | | | - include the correct folders - add a new buildscript for the common radeon folder v2: Use the installed libdrm headers over the DRM_TOP ones. Cc: "10.1 10.2" <[email protected]> [Emil Velikov] Split up and add commit message. Signed-off-by: Emil Velikov <[email protected]>
* radeon/uvd: fix gpu_address for video surfacesChristian König2014-08-121-0/+2
| | | | | | | | | | | We need to get the new gpu_address as well when reallocating the cs buffer. Bug: https://bugs.freedesktop.org/show_bug.cgi?id=82428 Signed-off-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Tested-by: Kai Wasserbäch <[email protected]>
* gallium: remove PIPE_SHADER_CAP_MAX_ADDRSMarek Olšák2014-08-111-3/+0
| | | | | | | | | | | | | | | This limit is fixed in Mesa core and cannot be changed. It only affects ARB_vertex_program and ARB_fragment_program. The minimum value for ARB_vertex_program is 1 according to the spec. The maximum value for ARB_vertex_program is limited to 1 by Mesa core. The value should be zero for ARB_fragment_program, because it doesn't support ARL. Finally, drivers shouldn't mess with these values arbitrarily. Reviewed-by: Ilia Mirkin <[email protected]>
* radeonsi: simplify constant buffer upload for big endianMarek Olšák2014-08-101-18/+4
| | | | | | | | Point util_memcpy_cpu_to_le32 to a buffer storage directly. v2: simplify more Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: fix CMASK and HTILE allocation on TahitiMarek Olšák2014-08-091-1/+54
| | | | | | | | | | | | | | | | Tahiti has 12 tile pipes, but P8 pipe config. It looks like there is no way to get the pipe config except for reading GB_TILE_MODE. The TILING_CONFIG ioctl doesn't return more than 8 pipes, so we can't use that for Hawaii. This fixes a regression caused by 9b046474c95f15338d4c748df9b62871bba6f36f on Tahiti. v2: add an assertion and print an error on failure Cc: [email protected] Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: use gpu_address from r600_resourceMarek Olšák2014-08-096-56/+41
| | | | | Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: always prefer SWITCH_ON_EOP(0) on CIKMarek Olšák2014-08-091-9/+24
| | | | | | | | | | | | | | The code is rewritten to take known constraints into account, while always using 0 by default. This should improve performance for multi-SE parts in theory. A debug option is also added for easier debugging. (If there are hangs, use the option. If the hangs go away, you have found the problem.) Reviewed-by: Alex Deucher <[email protected]> v2: fix a typo, set max_se for evergreen GPUs according to the kernel driver
* radeonsi: fix a hang with instancing in Unigine Heaven/Valley on HawaiiMarek Olšák2014-08-091-5/+2
| | | | | | | | This isn't documented anywhere, but it's the only thing that works for this case. Cc: [email protected] Reviewed-by: Alex Deucher <[email protected]>
* gallium/radeon: Add some Emacs .dir-locals.el filesMichel Dänzer2014-07-291-0/+11
| | | | | | Based on the toplevel one but adapted to the driver/winsys coding styles. Reviewed-by: Marek Olšák <[email protected]>
* r600g,radeonsi: switch all occurences of array_size to util_max_layerMarek Olšák2014-07-281-1/+1
| | | | | | | | | | | | | | | | | | This fixes 3D texture support in all these cases, because array_size is 1 with 3D textures and depth0 actually contains the "array size". util_max_layer is universal and returns the last layer index for any texture target. A lot of the cases below can't actually be hit with 3D textures, but let's be consistent. This fixes a failure in: piglit layered-rendering/clear-color-all-types 3d single_level for r600g and radeonsi, which was caused by an incorrect CMASK size calculation. Cc: [email protected] Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: fix a hang with streamout on HawaiiMarek Olšák2014-07-281-1/+13
| | | | | | | | | | | I actually couldn't reproduce this one, but internal docs recommend this workaround. Better safe than sorry. Also, the number of dwords for the sync packets is increased by 4 instead of 2, because it wasn't bumped last time when a new packet was added there. Cc: [email protected] Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: fix a hang with instancing on HawaiiMarek Olšák2014-07-281-1/+15
| | | | | | | This fixes "piglit/bin/arb_transform_feedback2-draw-auto instanced". Cc: [email protected] Reviewed-by: Alex Deucher <[email protected]>
* gallium: rename shader cap MAX_CONSTS to MAX_CONST_BUFFER_SIZEMarek Olšák2014-07-281-2/+2
| | | | | | | | | | This new name isn't so confusing. I also changed the gallivm limit, because it looked wrong. Reviewed-by: Brian Paul <[email protected]> v2: use sizeof(float[4])
* radeonsi: Use util_memcpy_cpu_to_le32()Tom Stellard2014-07-282-19/+8
| | | | Reviewed-by: Marek Olšák <[email protected]>
* r600g/radeonsi: Use write-combined CPU mappings of some BOs in GTTMichel Dänzer2014-07-231-1/+1
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/compute: Add support scratch buffer support v2Tom Stellard2014-07-213-2/+85
| | | | | | | | The scratch buffer will be used for private memory and also register spilling. v2: - Code cleanups
* radeonsi/compute: Bump number of user sgprs for LLVM 3.5Tom Stellard2014-07-211-1/+6
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/compute: Share COMPUTE_DBG macro with r600gTom Stellard2014-07-211-0/+5
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Read rodata from ELF and append it to the end of shadersTom Stellard2014-07-211-1/+12
| | | | | | | The is used for programs that have arrays of constants that are accessed using dynamic indices. The shader will compute the base address of the constants and then access them using SMRD instructions.
* radeonsi: only update vertex buffers when they need updatingMarek Olšák2014-07-183-2/+22
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: remove nr_vertex_buffersMarek Olšák2014-07-183-6/+23
| | | | | | | | Unused. Also inline util_set_vertex_buffers_count and simplify it. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: move vertex buffer descriptors from IB to memoryMarek Olšák2014-07-187-106/+133
| | | | | | | | | | This removes the intermediate storage (pm4 state) and generates descriptors directly in a staging buffer. It also reduces the number of flushes, because the descriptors no longer take CS space. Reviewed-by: Michel Dänzer <[email protected]>
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