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* radeonsi: emit string markers to log contextNicolai Hähnle2017-08-221-0/+3
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: log decompress blitsNicolai Hähnle2017-08-221-0/+13
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: log draw and compute state into log contextNicolai Hähnle2017-08-224-32/+51
| | | | | | Also add missing trace emits and CS logging for compute launches. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: print saved CS to the log contextNicolai Hähnle2017-08-225-88/+263
| | | | | | | | | | | | Use the auto logger facility, so that CS chunks will be interleaved with other log info. v2: - fix some crashes when not using CE - fix skipping "previous" chunks of current (unflushed) IB - fix error handling in si_begin_cs_debug Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: start using u_log_context for debuggingNicolai Hähnle2017-08-221-64/+175
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: re-order debug state dumpingNicolai Hähnle2017-08-221-7/+8
| | | | | | Keep together the parts that won't use the deferred logging mechanism. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: make si_shader_selector_reference globally visibleNicolai Hähnle2017-08-222-15/+16
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: add reference count to si_computeNicolai Hähnle2017-08-222-10/+28
| | | | | | To allow keep-alive for deferred logging. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: implement pipe_context::set_log_contextNicolai Hähnle2017-08-221-0/+9
| | | | | | | | We'll add radeonsi-specific code to set_log_context in later patches, but we may want to log from common code. Hence keep the log pointer in r600_common_context. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: don't prefetch VBO descriptors if vertex elements == NULLMarek Olšák2017-08-212-1/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* Android: Fix LLVM duplicated symbols linking for N and MRob Herring2017-08-211-1/+1
| | | | | | | | | | | | | | | | | | | | | Both statically linking libLLVMCore and dynamically linking libLLVM causes duplicated symbols in gallium_dri.so and it fails to dlopen. We don't really need to link libLLVMCore, but just need generated headers to be built first. Dynamically linking to libLLVM instead is enough to do that. Thanks to Qiang Yu for finding the root cause. With this change, we can align all versions and just have libLLVM as a shared lib dependency. This also requires changes in the M and N versions of LLVM to export the include paths for libLLVM. AOSP master is okay. Fixes: 26aee6f4d5a ("Android: rework LLVM build support") Reported-by: Mauro Rossi <[email protected]> Cc: 17.2 <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Signed-off-by: Qiang Yu <[email protected]> Signed-off-by: Rob Herring <[email protected]>
* radeon/uvd: add YUYV format support for target bufferLeo Liu2017-08-211-1/+1
| | | | | | | Make chroma plane optional for YUYV support Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeonsi: update non-resident bindless descriptors if neededSamuel Pitoiset2017-08-211-30/+55
| | | | | | | | | | Only resident bindless descriptors are currently updated and re-uploaded, this makes sure that the non-resident ones are also updated. Signed-off-by: Samuel Pitoiset <[email protected]> Cc: "17.2" <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: remove old_fence parameter from r600_gfx_write_event_eopMarek Olšák2017-08-182-3/+2
| | | | | | just use the new scratch buffer. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: prevent a GPU hang after a timestamp eventMarek Olšák2017-08-182-3/+3
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: don't use CLEAR_STATE on SIMarek Olšák2017-08-184-10/+63
| | | | | | | | | This fixes random hangs with Unigine Valley. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102201 Fixes: 064550238ef0 ("radeonsi: use CLEAR_STATE to initialize some registers") Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: disable CE by defaultMarek Olšák2017-08-151-6/+18
| | | | | | | | | It makes performance worse by a very small (hard to measure) amount. We've done extensive profiling of this feature internally. Cc: 17.1 17.2 <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Acked-by: Christian König <[email protected]>
* radeonsi/gfx9: fix the scissor bug workaroundMarek Olšák2017-08-111-3/+7
| | | | | | | | otherwise there is corruption in most apps. Fixes: 0fe0320 radeonsi: use optimal packet order when doing a pipeline sync Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: use the VI codepath for clamping ZMarek Olšák2017-08-112-12/+2
| | | | | | | | | This fixes corrupted shadows in Unigine Valley. The corruption disappeared when I stopped setting IMG_DATA_FORMAT_24_8 for depth. Cc: 17.2 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* ac: fail shader compilation if libelf is replaced by an incompatible versionMarek Olšák2017-08-101-1/+4
| | | | | | | | | | | | UE4Editor has this issue. This commit prevents hangs (release build) or assertion failures (debug build). It doesn't fix the editor, but catastrophic scenarios are prevented. Cc: 17.1 17.2 <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: drop two unused variables in create_function()Samuel Pitoiset2017-08-091-2/+0
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: fix a compile failure due to disabled assertsMarek Olšák2017-08-071-1/+1
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* radeonsi: use optimal packet order when doing a pipeline syncMarek Olšák2017-08-071-34/+83
| | | | | | | | | | | | Process most new SET packets in parallel with previous draw calls, then flush caches and wait, start the draw, and do L2 prefetches last. This decreases the [CP busy / SPI busy] ratio (verified with GRBM perf counters). In other words, the time window when shaders are idle (between (the wait and the draw) is much shorter now. Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: expose the number of decompress calls to the HUDMarek Olšák2017-08-071-7/+11
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: rename shader_userdata -> shader_pointers where appropriateMarek Olšák2017-08-075-20/+20
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: prefetch VBO descriptors after the first VGT shaderMarek Olšák2017-08-071-17/+63
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add a separate dirty mask for prefetchesMarek Olšák2017-08-076-16/+64
| | | | | | | | | | so that we don't rely on si_pm4_state_enabled_and_changed, allowing us to move prefetches after draw calls. v2: ckear the dirty mask after unbinding shaders Tested-by: Dieter Nützel <[email protected]> (v1) Reviewed-by: Nicolai Hähnle <[email protected]> (v1)
* radeonsi: add and use si_pm4_state_enabled_and_changedMarek Olšák2017-08-073-17/+18
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: de-atomize L2 prefetchMarek Olšák2017-08-077-9/+11
| | | | | | | I'd like to be able to move the prefetch call site around. Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: align all CE dumps to L2 cache line sizeMarek Olšák2017-08-071-8/+17
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove a tautology sctx->framebuffer.nr_samples >= 1Marek Olšák2017-08-071-2/+1
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: enable support for EXT_memory_objectAndres Rodriguez2017-08-061-1/+1
| | | | | | | | | v2: fix an indentation error v3: don't enable for r600 Signed-off-by: Andres Rodriguez <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* radeonsi: hook up device/driver UUID queriesAndres Rodriguez2017-08-061-0/+14
| | | | | | | v2: move from r600_common to radeonsi Signed-off-by: Andres Rodriguez <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* android: radeonsi: add nir include pathsMauro Rossi2017-08-041-1/+2
| | | | | | | | | | | | | | Android build changes to avoid the following building error: target C: libmesa_pipe_radeonsi <= external/mesa/src/gallium/drivers/radeonsi/si_pipe.c ... In file included from external/mesa/src/gallium/drivers/radeonsi/si_pipe.c:38: external/mesa/src/compiler/nir/nir.h:48:10: fatal error: 'nir_opcodes.h' file not found ^ 1 error generated. Fixes: da62a31c5b "radeonsi: add nir include paths" Reviewed-by: Emil Velikov <[email protected]>
* radeonsi: set drirc compiler options before calling common screen initNicolai Hähnle2017-08-041-4/+10
| | | | | | | | Also, access the options directly, allowing us to get rid of the PIPE_SCREEN_xxx flags. Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Makefile.sources: include driinfo_radeonsi.hJuan A. Suarez Romero2017-08-041-0/+1
| | | | Reviewed-by: Emil Velikov <[email protected]>
* radeonsi: program tile swizzle for color and FMASK surfaces for GFX & SDMAMarek Olšák2017-08-043-3/+29
| | | | | Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: if FMASK is disabled, set CB_COLORi_FMASK = CB_COLORi_BASE properlyMarek Olšák2017-08-041-1/+5
| | | | | Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* android: radeonsi: prepare for driver-specific driconf optionsMauro Rossi2017-08-031-0/+17
| | | | | | | | | | | | | Android build changes to avoid the following building error: In file included from external/mesa/src/gallium/targets/dri/target.c:1: external/mesa/src/gallium/auxiliary/target-helpers/drm_helper.h:185:10: fatal error: 'radeonsi/si_driinfo.h' file not found ^ 1 error generated. Fixes: 0f8c5de869 "radeonsi: prepare for driver-specific driconf options" Reviewed-by: Emil Velikov <[email protected]>
* gallium: introduce PIPE_CAP_MEMOBJTimothy Arceri2017-08-031-0/+1
| | | | | | | | | | | | | | This can be used to guard support for EXT_memory_object and related extensions. v2: update gallium docs v3 (Timothy Arceri): - add cap to nv50 Signed-off-by: Andres Rodriguez <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: add enable_sisched driconf optionNicolai Hähnle2017-08-022-0/+7
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: prepare for driver-specific driconf optionsNicolai Hähnle2017-08-023-0/+18
| | | | Reviewed-by: Marek Olšák <[email protected]>
* gallium: add pipe_screen_config to screen_create functionsNicolai Hähnle2017-08-022-3/+3
| | | | | | | This allows a more generic mechanism for passing user configurations into drivers by accessing the dri options directly. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: enable ARB_transform_feedback_overflow_queryNicolai Hähnle2017-08-021-1/+1
| | | | | | v2: update for new cap name Reviewed-by: Marek Olšák <[email protected]>
* gallium: add PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE and corresponding capNicolai Hähnle2017-08-021-0/+1
| | | | | | | | v2: rename cap to PIPE_CAP_QUERY_SO_OVERFLOW and be a bit more explicit in the documentation Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeon/ac: use ds_swizzle for derivs on si/cik.Dave Airlie2017-08-021-15/+1
| | | | | | | | | | | | This looks like it's supported since llvm 3.9 at least, so switch over radeonsi and radv to using it, -pro also uses this. We can now drop creating lds for these operations as the ds_swizzle operation doesn't actually write to lds at all. Acked-by: Marek Olšák <[email protected]> (stable requested due to fixing radv CIK conformance tests) Cc: [email protected] Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: print CE IBs into ddebug reportsMarek Olšák2017-08-014-6/+34
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: fix printing vertex buffer descriptors into ddebug reportsMarek Olšák2017-08-012-0/+8
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: don't flush sL1 conditionally in WAIT_ON_CE_COUNTERMarek Olšák2017-08-011-3/+3
| | | | | | | | I don't know the condition for the flush, but we better turn this off. The sL1 flush is used when CE dumps stuff into a ring buffer and the ring buffer wraps. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: set up HTILE in descriptors only when level 0 is accessibleMarek Olšák2017-08-011-1/+1
| | | | | | Compression isn't enabled with non-zero levels. Reviewed-by: Nicolai Hähnle <[email protected]>
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