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path: root/src/gallium/drivers/radeonsi/si_state_draw.c
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* radeonsi/gfx9: draw changesMarek Olšák2017-03-301-12/+31
* radeonsi/gfx9: add a scissor bug workaroundMarek Olšák2017-03-301-0/+6
* radeonsi: handle MultiDrawIndirect in si_get_draw_start_countNicolai Hähnle2017-02-211-7/+53
* gallium/u_index_modify: don't add PIPE_TRANSFER_UNSYNCHRONIZED unconditionallyMarek Olšák2017-02-191-1/+1
* radeonsi: fix UNSIGNED_BYTE index buffer fallback with non-zero start (v2)Marek Olšák2017-02-191-2/+2
* radeonsi: use a clever alignment for index buffer uploadsMarek Olšák2017-02-181-4/+7
* radeonsi: move index buffer flushing into a non-upload indexed caseMarek Olšák2017-02-181-7/+6
* gallium/radeon: remove the internal u_upload_mgr pointerMarek Olšák2017-02-141-2/+4
* radeonsi: remove SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFERMarek Olšák2017-02-101-1/+2
* radeonsi: remove separate CB/DB_META flush flagsMarek Olšák2017-02-101-10/+5
* gallium/radeon: merge dirty_fb_counter and dirty_tex_descriptor_counterMarek Olšák2017-01-301-11/+5
* radeonsi: handle count_from_stream_output in a few IA_MULTI_VGT_PARAM casesMarek Olšák2017-01-301-2/+4
* radeonsi: fold info->indirect conditionals into the last one in draw_vboMarek Olšák2017-01-301-12/+13
* radeonsi: atomize the scratch buffer stateMarek Olšák2017-01-301-24/+0
* radeonsi: precompute IA_MULTI_VGT_PARAM values into a tableMarek Olšák2017-01-301-72/+120
* radeonsi: move VGT_VERTEX_REUSE_BLOCK_CNTL into shader states for PolarisMarek Olšák2017-01-301-19/+0
* radeonsi: use a bitmask for looping over dirty PM4 statesMarek Olšák2017-01-301-2/+15
* radeonsi: atomize L2 prefetchesMarek Olšák2017-01-301-36/+1
* radeonsi: update dirty_level_mask only after the first draw after FB changeMarek Olšák2017-01-301-24/+28
* radeonsi: always set the TCL1_ACTION_ENA when invalidating L2Marek Olšák2017-01-231-1/+2
* radeonsi: use a global dirty mask for shader pointersMarek Olšák2017-01-181-1/+1
* ac/debug: Move IB decode to common code.Bas Nieuwenhuizen2017-01-091-1/+3
* radeonsi: add TC L2 prefetch for shaders and VBO descriptorsMarek Olšák2017-01-061-1/+36
* radeonsi: add HUD queries for cache flush statsMarek Olšák2017-01-061-0/+5
* radeonsi: add a tess+GS hang workaround for VI dGPUsMarek Olšák2016-12-011-2/+10
* radeonsi: apply a tessellation bug workaround for SIMarek Olšák2016-12-011-0/+7
* radeonsi: apply a multi-wave workgroup SPI bug workaround to affected CIK chipsMarek Olšák2016-12-011-2/+4
* radeonsi: fast exit si_emit_derived_tess_state earlyMarek Olšák2016-11-211-11/+14
* radeonsi: generate GS prolog to (partially) fix triangle strip adjacency rota...Nicolai Hähnle2016-11-031-0/+18
* gallium/radeon: use r600_gfx_write_event_eop everywhereMarek Olšák2016-10-261-9/+3
* radeonsi: implement TC-compatible HTILEMarek Olšák2016-10-131-1/+2
* radeonsi: use TC write-back instead of full cache invalidationMarek Olšák2016-10-121-3/+3
* radeonsi: implement TC L2 write-back (flush) without cache invalidationMarek Olšák2016-10-121-19/+62
* radeonsi: remove unnecessary #includesMarek Olšák2016-10-041-2/+0
* radeonsi: separate IA_MULTI_VGT_PARAM and VGT_PRIMITIVE_TYPE emissionMarek Olšák2016-10-041-7/+10
* radeonsi: move VGT_LS_HS_CONFIG to derived tess_stateMarek Olšák2016-10-041-26/+14
* radeonsi: Fix primitive restart when index changesJames Legg2016-10-041-7/+7
* radeonsi: fix the VGT performance tweak for small instancesMarek Olšák2016-09-091-5/+6
* radeonsi: remove the cache_flush atomMarek Olšák2016-09-091-5/+5
* radeonsi: skip redundant INDEX_TYPE writesMarek Olšák2016-09-071-20/+30
* radeonsi: add more unlikely() uses into si_draw_vboMarek Olšák2016-09-071-5/+5
* radeonsi: skip draws with instance_count == 0Marek Olšák2016-09-071-3/+13
* radeonsi: fix variable naming in si_emit_cache_flushMarek Olšák2016-09-051-31/+31
* radeonsi: don't emit CS_PARTIAL_FLUSH if compute is not usedMarek Olšák2016-09-051-1/+3
* radeonsi: add HUD queries for counting VS/PS/CS partial flushesMarek Olšák2016-09-051-0/+8
* radeonsi: fix a badly implemented GS bug workaroundMarek Olšák2016-09-051-8/+13
* radeonsi: program additional multi draw parametersNicolai Hähnle2016-08-091-5/+25
* radeonsi: program the DRAWID SGPRNicolai Hähnle2016-08-091-2/+6
* radeonsi: remove an incorrect assertionNicolai Hähnle2016-08-091-2/+0
* radeonsi: flush TC L2 cache for indirect draw dataNicolai Hähnle2016-08-091-0/+5
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