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path: root/src/gallium/drivers/radeonsi/si_state.c
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* radeonsi: add support for Vega12Marek Olšák2018-03-281-1/+3
| | | | Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: mask out high VM address bits in registers where neededMarek Olšák2018-03-071-11/+13
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* radv/radeonsi: set dcc min uncompressed properly for APUs.Dave Airlie2017-12-271-0/+9
| | | | | | | This is ported from amdvlk. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* amd/common/radv/radeonsi: use register defines for dcc block sizes.Dave Airlie2017-12-271-3/+3
| | | | | | | | These are just taken from amdvlk, we probably knew these already, but may as well port them now. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: set PNT_SPRITE_ENA = point_quad_rasterizationMarek Olšák2017-12-251-1/+1
| | | | This is based on how nvc0 translates the state.
* radeonsi: remove r600_common_screenMarek Olšák2017-11-291-46/+46
| | | | | | | | | | Most files in gallium/radeon now include si_pipe.h. chip_class and family are now here: sscreen->info.family sscreen->info.chip_class Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove query/apply_opaque_metadata callbacksMarek Olšák2017-11-291-98/+0
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove R600_CONTEXT_* flagsMarek Olšák2017-11-291-4/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove some definitions and helpers from r600_pipe_common.hMarek Olšák2017-11-291-9/+37
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: enable DCC with MSAA for VIMarek Olšák2017-11-291-1/+2
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add a workaround for blending with DCC and MSAAMarek Olšák2017-11-291-8/+23
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: cleanup si_initialize_color_surfaceNicolai Hähnle2017-11-281-12/+12
| | | | Reviewed-by: Marek Olšák <[email protected]>
* amd/common: sid.h cleanupsNicolai Hähnle2017-11-281-1/+1
| | | | | | | Fix a bunch of labels indicating when registers were added/removed and normalize the SI-class GRBM_GFX_INDEX. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: handle imported textures with DCC robustlyMarek Olšák2017-11-251-1/+1
| | | | | | | now you can hack the driver to enable DCC for displayable textures and Glamor that doesn't enable that by default won't crash anymore. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove 'Authors:' commentsMarek Olšák2017-11-021-3/+0
| | | | | | | It's inaccurate. Instead, see the copyright and use "git log" and "git blame" to know the authorship. Acked-by: Nicolai Hähnle <[email protected]>
* radeonsi: hardcode shader WAVE_LIMIT to the maximum valueAndres Rodriguez2017-10-211-7/+14
| | | | | | | | | | | | | This is part of a cooperative scheduling approach used by radv. All drivers in the stack must opt-in to resource arbitration, otherwise GL based apps will be able to ignore system priorities. We always hardcode the field to its maximum value, instead of attempting to calculate an approximate usage. In testing, there were no benefits to using anything other than the maximum. Signed-off-by: Andres Rodriguez <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi: add support for PIPE_FORMAT_{X1,A1}R5G5B5_UNORMNicolai Hähnle2017-10-121-0/+8
| | | | | | Fixes dEQP-EGL.functional.image.modify.tex_rgb5_a1_tex_subimage_rgba8 Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: shrink r600d_common.h and stop using itMarek Olšák2017-10-091-13/+13
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: import cayman_msaa.c from drivers/radeonMarek Olšák2017-10-091-11/+68
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: import r600_streamout from drivers/radeonMarek Olšák2017-10-091-2/+2
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: simplify a loop in si_update_fb_dirtiness_after_renderingMarek Olšák2017-10-061-15/+11
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium: Remove util_format_s3tc_enabledMatt Turner2017-10-021-4/+0
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* radeonsi: adjust clip discard based on line width / point sizeNicolai Hähnle2017-10-021-1/+6
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: remove si_context::{scissor_enabled,clip_halfz}Nicolai Hähnle2017-10-021-2/+12
| | | | | | They are just copies of the rasterizer state. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: move and rename scissor and viewport state and functionsNicolai Hähnle2017-10-021-3/+3
| | | | | | v2: change GET_MAX_SCISSOR to SI_MAX_SCISSOR Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: fix maximum advertised point size / line widthNicolai Hähnle2017-10-021-2/+2
| | | | | | | | | | The hardware registers store the half-size/width in 12.4 fixed point format, so 8192 is the maximum. Fixes dEQP-GLES3.functional.rasterization.* Cc: [email protected] Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: fix border color translation for integer texturesNicolai Hähnle2017-09-291-14/+36
| | | | | | | | | | This fixes the extremely unlikely case that an application uses 0x80000000 or 0x3f800000 as border color for an integer texture and helps in the also, but perhaps slightly less, unlikely case that 1 is used as a border color. Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radeonsi: clamp border colors for upgraded depth texturesNicolai Hähnle2017-09-291-59/+60
| | | | | | | | | | | | | The hardware does this automatically for unorm formats, but we need to do it manually for unorm depth formats that have been upgraded to Z32_FLOAT. Fixes dEQP-GLES31.functional.texture.border_clamp.range_clamp.nearest_unorm_depth and others. Fixes: d4d9ec55c589 ("radeonsi: implement TC-compatible HTILE") Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radeonsi: clamp depth comparison value only for fixed point formatsNicolai Hähnle2017-09-291-0/+4
| | | | | | | | | | | | | | | | | | | The hardware usually does this automatically. However, we upgrade depth to Z32_FLOAT to enable TC-compatible HTILE, which means the hardware no longer clamps the comparison value for us. The only way to tell in the shader whether a clamp is required seems to be to communicate an additional bit in the descriptor table. While VI has some unused bits in the resource descriptor, those bits have unfortunately all been used in gfx9. So we use an unused bit in the sampler state instead. Fixes dEQP-GLES3.functional.texture.shadow.2d.linear.equal_depth_component32f and many other tests in dEQP-GLES3.functional.texture.shadow.* Fixes: d4d9ec55c589 ("radeonsi: implement TC-compatible HTILE") Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* r600: fork and import gallium/radeonMarek Olšák2017-09-261-9/+9
| | | | | | | | | | | This marks the end of code sharing between r600 and radeonsi. It's getting difficult to work on radeonsi without breaking r600. A lot of functions had to be renamed to prevent linker conflicts. There are also minor cleanups. Acked-by: Dave Airlie <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: set MIP_POINT_PRECLAMP to 0Nicolai Hähnle2017-09-201-1/+1
| | | | | | | | | | | | | | | | | This fixes a bug with nearest ("point") mip selection when the fractional part of max_lod is in (0.5,1). In this case, the spec mandates that we still select the mip level ceil(max_lod) in the clamping case. However, MIP_POINT_PRECLAMP will clamp before the mip selection, which is wrong. Supposedly this setting was originally copied from the closed Vulkan driver, but as far as I can tell, closed Vulkan was actually changed back recently :) Fixes dEQP-GLES3.functional.texture.mipmap.2d.max_lod.{nearest,linear}_nearest Fixes: f7420ef5b464 ("radeonsi: enable some sampler fields to match the closed driver") Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radeonsi: allow out-of-order rasterization in commutative blending casesNicolai Hähnle2017-09-181-4/+63
| | | | | | | | | | | | We do not enable this by default for additive blending, since it slightly breaks OpenGL invariance guarantees due to non-determinism. Still, there may be some applications can benefit from white-listing via the radeonsi_commutative_blend_add drirc setting without any real visible artifacts. Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radeonsi: add drirc option "radeonsi_assume_no_z_fights"Nicolai Hähnle2017-09-181-4/+4
| | | | | | | | | | | | | | This option enables a performance optimization where typical non-blending draws with depth buffer may be rasterized out-of-order (on VI+, multi-SE chips). This optimization can lead to incorrect results when an applications renders multiple objects with the same Z value at the same pixel, so we will never enable it by default. But there may be applications that could benefit from white-listing. Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radeonsi: enable out-of-order rasterization when possible on VI and GFX9 dGPUsNicolai Hähnle2017-09-181-2/+155
| | | | | | | | | This does not take commutative blending into account yet. R600_DEBUG=nooutoforder disables it. Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* gallium/radeon: pass old_(perfect_)enable to set_occlusion_query_stateNicolai Hähnle2017-09-181-1/+3
| | | | | | | The callee can derive the current enable state itself. Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* gallium/{r600, radeonsi}: Fix segfault with color format (v2)Denis Pauk2017-09-141-1/+9
| | | | | | | | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102552 v2: Patch cleanup proposed by Nicolai Hähnle. * deleted changes in si_translate_texformat. Cc: Nicolai Hähnle <[email protected]> Cc: Ilia Mirkin <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeonsi: rename variable to clarify its meaningNicolai Hähnle2017-09-131-10/+10
| | | | Reviewed-by: Marek Olšák <[email protected]>
* ac/surface: add radeon_surf::has_stencil for convenienceMarek Olšák2017-09-071-4/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: always flush DB metadata on framebuffer changesNicolai Hähnle2017-09-061-1/+10
| | | | | | | This fixes GL45-CTS.shader_image_load_store.basic-glsl-earlyFragTests. Cc: [email protected] Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/gfx9: implement primitive binningMarek Olšák2017-09-051-6/+20
| | | | | | | This increases performance, but it was tuned for Raven, not Vega. We don't know yet how Vega will perform, hopefully not worse. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add more state flags into si_state_dsaMarek Olšák2017-09-051-0/+17
| | | | | | | 3 flags for primitive binning, 2 flags for out-of-order rasterization (but that will be done some other time) Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: don't use BREAK_BATCH and FLUSH_DFSM if DFSM is disabledMarek Olšák2017-09-051-3/+3
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: eliminate PS color outputs when colormask kills themMarek Olšák2017-09-041-0/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: rewrite late alloc VS limit computationMarek Olšák2017-08-281-12/+25
| | | | | | This is still very simple, but it's better than before. Loosely ported from Vulkan.
* Revert "radeonsi: get the raster config from AMDGPU on SI"Marek Olšák2017-08-271-17/+0
| | | | | | | | | | | | This reverts commit fc99cb3c9edee3af773700cf7ebdc60dc02fcaba. "The performance went down from 64.7 to 51.4 fps in Valley and from 30.8 to 25.1 fps in Heaven on Radeon HD 7970. Other games seem to have also a 10-25% performance decrease." Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102429 It looks like we can't use the raster config values from the kernel.
* radeonsi: get the raster config from AMDGPU on SIMarek Olšák2017-08-241-0/+17
| | | | | | Not sure yet if we wanna do this on CIK and VI too. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: clean up setting GRBM_GFX_INDEXMarek Olšák2017-08-241-19/+22
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move PA_SC_RASTER_CONFIG emission into a separate functionMarek Olšák2017-08-241-70/+73
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: emit VGT_REUSE_OFF in the right placeMarek Olšák2017-08-221-6/+0
| | | | | | | clip_regs aren't marked dirty when writes_viewport_index is changed. Cc: 17.2 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: add helpers for whether HTILE is enabledMarek Olšák2017-08-221-5/+3
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
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