| Commit message (Collapse) | Author | Age | Files | Lines |
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This is the last use tgsi_parse_token in radeonsi.
It looks ugly because the code was re-indented, but there is really no change
in behavior.
Reviewed-by: Michel Dänzer <[email protected]>
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It's redundant now.
It led to a simplification in si_llvm_emit_streamout, because outidx == reg.
Reviewed-by: Michel Dänzer <[email protected]>
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That code was really ugly.
Reviewed-by: Michel Dänzer <[email protected]>
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They were reinventing tgsi_shader_info. They are unused now.
radeon_llvm_context::load_input can be NULL if input fetching is implemented
in some other way.
Reviewed-by: Michel Dänzer <[email protected]>
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Those are going away.
Reviewed-by: Michel Dänzer <[email protected]>
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Reviewed-by: Michel Dänzer <[email protected]>
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Reviewed-by: Michel Dänzer <[email protected]>
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Reviewed-by: Michel Dänzer <[email protected]>
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Reviewed-by: Michel Dänzer <[email protected]>
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tgsi_shader_info contains everything we need.
Reviewed-by: Michel Dänzer <[email protected]>
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Both cases are equivalent.
Reviewed-by: Michel Dänzer <[email protected]>
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Written CLIPDIST outputs are simply disabled in PA_CL_VS_OUT_CNTL.
Reviewed-by: Michel Dänzer <[email protected]>
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No code in Mesa sets the usage mask to any other value.
The final mask is AND'ed with enable bits from the rasterizer state anyway.
If somebody implements setting usage masks in st/mesa, we can use
tgsi_shader_info to get it more easily.
This is a prerequisite for the following commit.
Reviewed-by: Michel Dänzer <[email protected]>
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Reviewed-by: Roland Scheidegger <[email protected]>
v2: fix svga too
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It only needs the constant buffer with clip planes and read-write resources
for the GS->VS ring and streamout. That's 2 pointers.
Reviewed-by: Michel Dänzer <[email protected]>
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Reviewed-by: Michel Dänzer <[email protected]>
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I hope this is correct.
Reviewed-by: Michel Dänzer <[email protected]>
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st/mesa has the same flag in its shader key, we don't need to do it
in the driver anymore.
Instead, use TGSI_INTERPOLATE_LOC_SAMPLE, which is what st/mesa sets.
Reviewed-by: Michel Dänzer <[email protected]>
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Reviewed-by: Michel Dänzer <[email protected]>
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Reviewed-by: Michel Dänzer <[email protected]>
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Reviewed-by: Michel Dänzer <[email protected]>
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Use an array of properties indexed by TGSI_PROPERTY_* definitions.
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Reviewed-by: Michel Dänzer <[email protected]>
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Cc: 10.2 10.3 <[email protected]>
Reviewed-by: Michel Dänzer <[email protected]>
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This should prevent accessing context state there.
Reviewed-by: Michel Dänzer <[email protected]>
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Instead, pass the layout of GS inputs in memory to the ES using the shader
key. Only 64 bits are needed to represent the layout in the key.
Mixing and matching different VS and GS shaders should now always work.
Reviewed-by: Michel Dänzer <[email protected]>
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This was the original naming convention in r600g and it somehow crept
into radeonsi.
Reviewed-by: Michel Dänzer <[email protected]>
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One is part of the other anyway.
Reviewed-by: Michel Dänzer <[email protected]>
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Reviewed-by: Michel Dänzer <[email protected]>
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Also set the field on SI too. It's not just specific to CIK.
Reviewed-by: Michel Dänzer <[email protected]>
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- Add top_srcdir/src/gallium/winsys to GALLIUM_DRIVER_C{XXFLAGS}.
- Remove top_srcdir/src/gallium/drivers/radeon from the includes.
As a result:
- Common radeon headers are prefixed with 'radeon/'
- Winsys header inclusion is prefixed 'radeon/drm'
Cc: Marek Olšák <[email protected]>
Cc: Michel Dänzer <[email protected]>
Signed-off-by: Emil Velikov <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
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This hack isn't needed anymore because of the previous u_blitter commit.
Reviewed-by: Michel Dänzer <[email protected]>
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Reviewed-by: Marek Olšák <[email protected]>
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The scratch buffer will be used for private memory and also register
spilling.
v2:
- Code cleanups
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The is used for programs that have arrays of constants that
are accessed using dynamic indices. The shader will compute
the base address of the constants and then access them using
SMRD instructions.
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The draw indirect packets cannot set VGT_INDX_OFFSET, they can only set user
data SGPRs. This is the only way to support start/index_bias with indirect
drawing.
Reviewed-by: Michel Dänzer <[email protected]>
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Reviewed-by: Michel Dänzer <[email protected]>
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It indeed breaks LLVM 3.4.2.
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Reviewed-by: Tom Stellard <[email protected]>
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This is a follow-up to the commit which adds texture fetches with offsets.
Reviewed-by: Tom Stellard <[email protected]>
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Instead of using intr_name in lp_build_tgsi_action, this selects the names
with a switch statement in the emit function. This allows emitting
llvm.SI.sample for instructions without offsets and llvm.SI.image.sample.*.o
otherwise.
This depends on my LLVM changes.
When LLVM 3.5 is released, I'll switch all texture instructions to the new
intrinsics.
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Pack the depth value before overwriting it with cube coordinates.
Cc: [email protected]
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The new location field can be either center, centroid, or sample, which
indicates the location that the shader should interpolate at.
Signed-off-by: Ilia Mirkin <[email protected]>
Reviewed-by: Roland Scheidegger <[email protected]>
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Reviewed-by: Michel Dänzer <[email protected]>
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Reviewed-by: Michel Dänzer <[email protected]>
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reviewed by Michel Dänzer
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All ARB_texture_gather and gather-related ARB_gpu_shader5 piglit tests pass.
reviewed by Michel Dänzer
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This was wrong for a very long time. I wonder if the array size has any
effect on anything.
Reviewed-by: Christian König <[email protected]>
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