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path: root/src/gallium/drivers/radeonsi/si_pipe.c
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* radeonsi: add support for viewport array (v3)Dave Airlie2015-06-271-1/+1
| | | | | | | | | | | | | | | | | This isn't pretty and I'd suggest it the pm4 interface builder could be tweaked to do this more efficently, but I'd need guidance on how that would look. This seems to pass the few piglit tests I threw at it. v2: handle passing layer/viewport index to fragment shader. fix crash in blit changes, add support to io_get_unique_index for layer/viewport index update docs. v3: avoid looking up viewport index and layer in es (Marek). Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* tgsi/ureg: don't emit in/out arrays if drivers don't support ranged declarationsMarek Olšák2015-06-051-0/+1
| | | | | | Softpipe, llvmpipe, r300g, and radeonsi pass tests. Other drivers need testing. Freedreno and nv30 are definitely broken. Other drivers seem to be alright.
* radeonsi: add support for PIPE_CAP_TGSI_TEXCOORDMarek Olšák2015-05-261-1/+1
| | | | | | | | | | | | | Without it, texcoords are mapped to GENERIC[0..7], PointCoord is mapped to GENERIC[8], and user-defined varyings start from GENERIC[9]. Since texcoords can only be used between VS and PS, and PointCoord is PS-only, it's silly to always start from GENERIC[9] in all other shaders (such as LS, HS, ES, GS). This adds support for TEXCOORD and PCOORD semantics. As a result, st/mesa will use GENERIC[0] as a base for user-defined varyings, which should make linking ES and GS as well as tessellation shaders at runtime easier. Reviewed-by: Michel Dänzer <[email protected]>
* gallium: add PIPE_CAP_DEVICE_RESET_STATUS_QUERYMarek Olšák2015-05-121-0/+1
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* radeonsi: remove useless includesMarek Olšák2015-04-271-3/+0
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: remove bogus r600-- tripleEmil Velikov2015-04-161-2/+0
| | | | | | | | | | As mentioned by Michel Dänzer for LLVM >= 3.6 we create the LLVMTargetMachine (with triple amdgcn--), as we setup the radeonsi context. For older LLVM or hardware (r600) the triple is always r600-- and is created at a later stage - radeon_llvm_compile() Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi/compute: Default to the same PIPE_SHADER_CAP values as other shader ↵Tom Stellard2015-03-311-1/+5
| | | | | | | | | types v2 v2: - Fix typo Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Cache LLVMTargetMachineRef in context instead of in screenMichel Dänzer2015-03-301-20/+23
| | | | | | | | | | Fixes a crash in genymotion with several threads compiling shaders concurrently. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89746 Cc: 10.5 <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeonsi: move PA_SU_SC_MODE_CNTL to rasterizer stateMarek Olšák2015-03-161-1/+1
| | | | | | | | | This requires enabling the optional GL provoking vertex behavior for quads. + some cosmetic changes, so that the register is set exactly the same as on r600. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: split sample locations into its own state atomMarek Olšák2015-03-161-0/+3
| | | | | | Sample locations are not updated as often as framebuffers. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: add support for SQRTMarek Olšák2015-03-161-1/+1
| | | | | Reviewed-by: Tom Stellard <[email protected]> Reviewed-by: Glenn Kennard <[email protected]>
* radeonsi: add support for FMAMarek Olšák2015-03-161-1/+2
| | | | | Reviewed-by: Tom Stellard <[email protected]> Reviewed-by: Glenn Kennard <[email protected]>
* gallium: add FMA and DFMA opcodes (v3)Marek Olšák2015-03-161-0/+1
| | | | | | | | | Needed by ARB_gpu_shader5. v2: select DMAD for FMA with double precision v3: add and select DFMA Reviewed-by: Ilia Mirkin <[email protected]>
* radeonsi/compute: Enable PIPE_SHADER_CAP_DOUBLES v2Tom Stellard2015-02-271-2/+2
| | | | | | | v2: - Simplify ifdef Reviewed-by: Michel Dänzer <[email protected]>
* gallium: add shader cap for dldexp/dfracexp supportIlia Mirkin2015-02-191-0/+1
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* gallium: add a cap to enable double rounding opcodesIlia Mirkin2015-02-191-0/+1
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* r600g,radeonsi: implement GL_AMD_pinned_memoryMarek Olšák2015-02-171-0/+3
| | | | | | v2: update release notes Reviewed-by: Christian König <[email protected]>
* gallium: Add MULTISAMPLE_Z_RESOLVE capAxel Davy2015-02-061-0/+1
| | | | | | | | | | | | | | | | Resolving a multisampled depth texture into a single sampled texture is supported on >= SM4.1 hw. It is possible some previous hw support it. The ability was tested on radeonsi and nvc0. Apparently is is also supported for radeon >= r700. This patch adds the MULTISAMPLE_Z_RESOLVE cap and add it to the drivers. It is advertised for drivers for which it is sure the ability is supported. Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Axel Davy <[email protected]>
* radeonsi: implement polygon stipplingMarek Olšák2015-02-041-0/+2
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* gallium: add a cap to determine whether the driver supports offset_clampIlia Mirkin2015-02-021-0/+1
| | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Glenn Kennard <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* radeonsi: Enable VGPR spilling for all shader types v5Tom Stellard2015-01-281-1/+8
| | | | | | | | | | | | | | | | | | | | v2: - Only emit write SPI_TMPRING_SIZE once per packet. - Use context global scratch buffer. v3: - Patch shaders using WRITE_DATA packet instead of map/unmap. - Emit ICACHE_FLUSH, CS_PARTIAL_FLUSH, PS_PARTIAL_FLUSH, and VS_PARTIAL_FLUSH when patching shaders. v4: - Code cleanups. - Remove unnecessary multiplies. v5: - Patch shaders in system memory and re-upload to vram. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: Fix crash when destroying si_screenTom Stellard2015-01-071-2/+4
| | | | | | | | | We were invalidating si_screen:tm by calling r600_destroy_common_screen() which frees the si_screen object. This caused the driver to crash in LLVMDisposeTargetMachine() since we were passing it an invalid pointer. https://bugs.freedesktop.org/show_bug.cgi?id=88170
* radeonsi: only flush the right set of caches for CP DMA operationsMarek Olšák2015-01-071-1/+1
| | | | | | | | That's either framebuffer caches or caches for shader resources. The motivation is that framebuffer caches need to be flushed very rarely here. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: remove init config from statesMarek Olšák2015-01-071-0/+1
| | | | | | It really doesn't do anything there. Reviewed-by: Michel Dänzer <[email protected]>
* radeon/llvm: Use amdgcn triple for SI+ on LLVM >= 3.6Tom Stellard2015-01-061-2/+7
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* radeonsi: Cache LLVMTargetMachine object in si_screenTom Stellard2015-01-061-0/+17
| | | | | | | | | | Rather than building a new one every compile. This should reduce some of the overhead of compiling shaders. One consequence of this change is that we lose the MachineInstrs dumps when dumping the shaders via R600_DEBUG. The LLVM IR and assembly is still dumped, and if you still want to see the MachineInstr dump, you can run the dumped LLVM IR through llc.
* gallium: add TGSI_SEMANTIC_VERTEXID_NOBASE and TGSI_SEMANTIC_BASEVERTEXRoland Scheidegger2014-12-161-0/+1
| | | | | | | | | | | | | | | | | | | Plus a new PIPE_CAP_VERTEXID_NOBASE query. The idea is that drivers not supporting vertex ids with base vertex offset applied (so, only support d3d10-style vertex ids) will get such a d3d10-style vertex id instead - with the caveat they'll also need to handle the basevertex system value too (this follows what core mesa already does). Additionally, this is also useful for other state trackers (for instance llvmpipe / draw right now implement the d3d10 behavior on purpose, but with different semantics it can just do both). Doesn't do anything yet. And fix up the docs wrt similar values. v2: incorporate feedback from Brian and others, better names, better docs. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: move all shader-related functions to a new file si_state_shaders.cMarek Olšák2014-12-101-0/+1
| | | | | | This huge amount of code deserves its own file. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: support gl_FragCoord at integer pixel centerMarek Olšák2014-11-181-1/+1
| | | | | | No known benefit for OpenGL, but it doesn't hurt. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: implement TGSI_PROPERTY_VS_WINDOW_SPACE_POSITIONMarek Olšák2014-11-161-1/+1
| | | | | | | Required by Nine. Reviewed-by: Michel Dänzer <[email protected]> Tested-by: Nick Sarnie <[email protected]>
* radeonsi/compute: Enable PIPE_SHADER_IR_NATIVE for compute shaders v2Tom Stellard2014-10-311-0/+4
| | | | | | v2: - Drop dependency on LLVM >= 3.5.1 - Rename si_create_shader() to si_shader_binary_read()
* gallium: introduce PIPE_CAP_CLIP_HALFZ.Mathias Fröhlich2014-10-241-0/+1
| | | | | | | | | | | | In preparation of ARB_clip_control. Let the driver decide if it supports pipe_rasterizer_state::clip_halfz being set to true. v3: Initially enable on ilo. Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Froehlich <[email protected]
* gallium: add PIPE_SHADER_CAP_MAX_OUTPUTS and use it in st/mesaMarek Olšák2014-10-211-0/+2
| | | | | | | | With 5 shader stages and various combinations of enabled and disabled shaders, the maximum number of outputs in one shader doesn't have to be equal to the maximum number of inputs in the following shader. v2: return 32 for softpipe and llvmpipe
* radeonsi: fix CS tracing and remove excessive CS dumpingMarek Olšák2014-10-041-1/+2
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* radeonsi: release GS rings at context destructionMarek Olšák2014-09-241-0/+2
| | | | | Cc: 10.2 10.3 <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* r600g,radeonsi: add debug option which forces DMA for copy_region and blitMarek Olšák2014-09-121-0/+3
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* gallium: add a texture target to sampler view and a CAP to use itIlia Mirkin2014-09-121-0/+1
| | | | | | | | | | This allows a sampler view to have a different texture target than the underlying resource. This will be used to implement the type casting between 2d arrays and cube maps as specified in ARB_texture_view. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Compile dummy pixel shader on demandMichel Dänzer2014-09-021-7/+0
| | | | | | It's never used under normal circumstances. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: move DB_RENDER_CONTROL into draw_vboMarek Olšák2014-09-011-6/+1
| | | | | | So that I can add fast depth clear. Reviewed-by: Michel Dänzer <[email protected]>
* gallium: add cap for MAX_VERTEX_ATTRIB_STRIDETimothy Arceri2014-08-271-0/+3
| | | | | Signed-off-by: Timothy Arceri <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* gallium: Add and handle PIPE_CAP_CONDITIONAL_RENDER_INVERTEDTobias Klausmann2014-08-191-0/+1
| | | | | | Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Tobias Klausmann <[email protected]>
* radeonsi: use r600_draw_rectangle from r600gMarek Olšák2014-08-191-1/+1
| | | | | | Rectangles are easier than triangles for the rasterizer. Reviewed-by: Michel Dänzer <[email protected]>
* gallium/r300/r600/radeonsi: handle query_renderer capsEmil Velikov2014-08-151-0/+11
| | | | | Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium: add opcodes/cap for fine derivative supportIlia Mirkin2014-08-141-0/+1
| | | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]> (v1) Reviewed-by: Roland Scheidegger <[email protected]> (v1) v2: Reuse opcode gaps as suggested by Marek
* radeon/compute: Report a value for PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZETom Stellard2014-08-131-0/+7
| | | | CC: "10.2" <[email protected]>
* gallium: remove PIPE_SHADER_CAP_MAX_ADDRSMarek Olšák2014-08-111-3/+0
| | | | | | | | | | | | | | | This limit is fixed in Mesa core and cannot be changed. It only affects ARB_vertex_program and ARB_fragment_program. The minimum value for ARB_vertex_program is 1 according to the spec. The maximum value for ARB_vertex_program is limited to 1 by Mesa core. The value should be zero for ARB_fragment_program, because it doesn't support ARL. Finally, drivers shouldn't mess with these values arbitrarily. Reviewed-by: Ilia Mirkin <[email protected]>
* radeonsi: fix CMASK and HTILE allocation on TahitiMarek Olšák2014-08-091-1/+54
| | | | | | | | | | | | | | | | Tahiti has 12 tile pipes, but P8 pipe config. It looks like there is no way to get the pipe config except for reading GB_TILE_MODE. The TILING_CONFIG ioctl doesn't return more than 8 pipes, so we can't use that for Hawaii. This fixes a regression caused by 9b046474c95f15338d4c748df9b62871bba6f36f on Tahiti. v2: add an assertion and print an error on failure Cc: [email protected] Reviewed-by: Michel Dänzer <[email protected]>
* gallium: rename shader cap MAX_CONSTS to MAX_CONST_BUFFER_SIZEMarek Olšák2014-07-281-2/+2
| | | | | | | | | | This new name isn't so confusing. I also changed the gallivm limit, because it looked wrong. Reviewed-by: Brian Paul <[email protected]> v2: use sizeof(float[4])
* radeonsi: implement ARB_draw_indirectMarek Olšák2014-07-181-0/+1
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: assume LLVM 3.4.2 is always presentMarek Olšák2014-07-181-8/+4
| | | | Reviewed-by: Michel Dänzer <[email protected]>
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