summaryrefslogtreecommitdiffstats
path: root/src/gallium/drivers/radeonsi/si_pipe.c
Commit message (Collapse)AuthorAgeFilesLines
* radeonsi/gfx9: fix a hang with an empty first IBMarek Olšák2018-04-231-3/+6
| | | | | | | | This packet causes the no-op IB detection to fail, so the IB is always submitted. Also fix the no-op IB detection by moving the begin call. Cc: 18.0 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: make shader binaries use read-only memoryMarek Olšák2017-12-061-0/+2
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove r600_common_screenMarek Olšák2017-11-291-112/+110
| | | | | | | | | | Most files in gallium/radeon now include si_pipe.h. chip_class and family are now here: sscreen->info.family sscreen->info.chip_class Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove r600_pipe_common::barrier_flags::compute_to_L2Marek Olšák2017-11-291-2/+0
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: dismantle si_common_screen_init/destroyMarek Olšák2017-11-291-3/+98
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: set all pipe buffer functions in r600_buffer_common.cMarek Olšák2017-11-291-1/+2
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move/remove ac_shader_binary helpersMarek Olšák2017-11-291-1/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move all get functions to si_get.c; disk_cache_create to si_pipe.cMarek Olšák2017-11-291-442/+44
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove r600_common_context::clear_bufferMarek Olšák2017-11-291-3/+3
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move r600_test_dma.c into si_test_dma.cMarek Olšák2017-11-291-1/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move all clear() code into si_clear.cMarek Olšák2017-11-291-0/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: enable DCC with MSAA for VIMarek Olšák2017-11-291-0/+5
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove has_cp_dma, has_streamout flags (v2)Marek Olšák2017-11-141-3/+0
| | | | v2: remove r600_can_dma_copy_buffer
* gallium: add CAPs to support HW atomic counters. (v3)Dave Airlie2017-11-101-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | This looks like an evergreen specific feature, but with atomic counters AMD have hw specific counters they use instead of operating on buffers directly. These are separate to the buffer atomics, so require different limits and code paths. I've left the CAP for atomic type extensible in case someone else has a variant on this sort of thing (freedreno maybe?) and needs to change it. This adds all the CAPs required to add support for those atomic counters, along with a related CAP for limiting the number of output resources. I'd like to land this and the st patch then I can start to upstream the evergreen support for these and other GL4.x features. v2: drop the ATOMIC_COUNTER_MODE cap, just use the return from the HW counters. If 0 we use the current mode. v3: fix some rebase errors (Gert Wollny) Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Tested-By: Gert Wollny <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: use a threaded context even for debug contextsNicolai Hähnle2017-11-091-9/+2
| | | | Reviewed-by: Marek Olšák <[email protected]>
* gallium/u_threaded: implement asynchronous flushesNicolai Hähnle2017-11-091-0/+3
| | | | | | | | | | | | | This requires out-of-band creation of fences, and will be signaled to the pipe_context::flush implementation by a special TC_FLUSH_ASYNC flag. v2: - remove an incorrect assertion - handle fence_server_sync for unsubmitted fences by relying on the improved cs_add_fence_dependency - only implement asynchronous flushes on amdgpu Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: move fence functions to si_fence.cNicolai Hähnle2017-11-091-0/+2
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: fix potential use-after-free of debug callbacksNicolai Hähnle2017-11-091-0/+4
| | | | | | Found by inspection. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: move pipe debug callback to si_contextNicolai Hähnle2017-11-091-0/+12
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: add si_screen::has_ls_vgpr_init_bugMarek Olšák2017-11-071-0/+2
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: use ac_create_target_machineMarek Olšák2017-11-071-15/+7
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: use ac_get_llvm_processor_nameMarek Olšák2017-11-071-2/+2
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: don't set gs_table_depthMarek Olšák2017-11-071-2/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: enable signed vertex buffer offsetsMarek Olšák2017-11-061-1/+1
|
* gallium: add PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSETMarek Olšák2017-11-061-0/+1
|
* gallium: add cap for driver specified max combined shader resources.Dave Airlie2017-11-011-0/+1
| | | | | | | | Some hw (evergreen) has a limit on how many combined (images/buffers/mrts) a fragment shader can access. Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: update hack for HTILE corruption in ARK: Survival EvolvedSamuel Pitoiset2017-10-271-2/+2
| | | | | | | | | | | | It appears that flushing the DB metadata is actually not sufficient since the driver uses the new VS blit shaders. This looks quite strange though, but it seems like we need to flush DB for fixing the corruption. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102955 Fixes: 69ccb9dae7 (radeonsi: use new VS blit shaders (VS inputs in SGPRs) Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: implement sync_file import/exportMarek Olšák2017-10-121-1/+3
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: lower ffma in nir to mad.Dave Airlie2017-10-111-0/+1
| | | | | | | | | | | This lowers ffma to a * b + c. This seems like it should keep Marek happiest, so we'd never get to the fma instruction emission code. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* gallium: Create a new PIPE_CAP_TILE_RASTER_ORDER for vc4.Eric Anholt2017-10-101-0/+1
| | | | | | | | | | | | | | | | Because vc4 can control the order that tiles are rasterized in, we can use it to implement overlapping blits using normal drawing and GL_ARB_texture_barrier, as long as we can tell the kernel what order to render the tiles in. This commit introduces the core gallium support, vc4 changes will follow. v2: Fix on the simulator. v3: Add the cap (disabled) to other drivers, add rst docs for the cap. v4: Rebase on PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS v5: Drop vc4 changes from this commit, for clarity. Reviewed-by: Nicolai Hähnle <[email protected]> (v3)
* radeonsi: import cayman_msaa.c from drivers/radeonMarek Olšák2017-10-091-0/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: import r600_streamout from drivers/radeonMarek Olšák2017-10-091-0/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: disable primitive binning on Vega10 (v2)Marek Olšák2017-10-091-4/+15
| | | | | | | | | | | | | | | Our driver implementation is known to decrease performance for some tests, but we don't know if any apps and benchmarks (e.g. those tested by Phoronix) are affected. This disables the feature just to be safe. Set this to enable partial primitive binning: R600_DEBUG=dpbb Set this to enable full primitive binning: R600_DEBUG=dpbb,dfsm v2: add new debug options Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: enumerize DBG flagsMarek Olšák2017-10-091-19/+19
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: don't change viewport for blits, use window-space positionsMarek Olšák2017-10-071-0/+1
| | | | | | The viewport state was an identity anyway. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add VS blit shader creationMarek Olšák2017-10-071-0/+10
| | | | | | no users yet Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add a drirc workaround for HTILE corruption in ARK: Survival EvolvedMarek Olšák2017-10-061-0/+2
| | | | | | | | v2: use DB_META | PS_PARTIAL_FLUSH Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102955 Reviewed-by: Samuel Pitoiset <[email protected]> (v1) Reviewed-by: Nicolai Hähnle <[email protected]> (v1)
* radeonsi: implement PIPE_CAP_TGSI_ANY_REG_AS_ADDRESSMarek Olšák2017-10-061-3/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium: add PIPE_CAP_TGSI_ANY_REG_AS_ADDRESSMarek Olšák2017-10-061-0/+1
| | | | | Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move and rename scissor and viewport state and functionsNicolai Hähnle2017-10-021-1/+2
| | | | | | v2: change GET_MAX_SCISSOR to SI_MAX_SCISSOR Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: emit DLDEXP and DFRACEXP TGSI opcodesNicolai Hähnle2017-09-291-1/+1
| | | | | | | | | Note: this causes spurious regressions in some current piglit tests, because the tests incorrectly assume that there is no denorm support for doubles. I'm going to send out a fix for those tests as well. Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radeonsi: emit LDEXP opcodeNicolai Hähnle2017-09-291-1/+1
| | | | | | | | The LLVM intrinsic has existed for a long time. The current name was established in LLVM 3.9. Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* gallium: add LDEXP TGSI instruction and corresponding capNicolai Hähnle2017-09-291-0/+1
| | | | | Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* r600: fork and import gallium/radeonMarek Olšák2017-09-261-12/+12
| | | | | | | | | | | This marks the end of code sharing between r600 and radeonsi. It's getting difficult to work on radeonsi without breaking r600. A lot of functions had to be renamed to prevent linker conflicts. There are also minor cleanups. Acked-by: Dave Airlie <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium: Add PIPE_SHADER_CAP_INT64_ATOMICSJan Vesely2017-09-211-0/+1
| | | | | | | Denotes availability of 64bit int atomic instructions Signed-off-by: Jan Vesely <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium: Add PIPE_SHADER_CAP_FP16Jan Vesely2017-09-181-0/+1
| | | | | | | | | Denotes native half precision float operations capability v2: PIPE_CAP_HALFS -> PIPE_SHADER_CAP_FP16 fix indentation Signed-off-by: Jan Vesely <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: allow out-of-order rasterization in commutative blending casesNicolai Hähnle2017-09-181-0/+2
| | | | | | | | | | | | We do not enable this by default for additive blending, since it slightly breaks OpenGL invariance guarantees due to non-determinism. Still, there may be some applications can benefit from white-listing via the radeonsi_commutative_blend_add drirc setting without any real visible artifacts. Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radeonsi: add drirc option "radeonsi_assume_no_z_fights"Nicolai Hähnle2017-09-181-0/+2
| | | | | | | | | | | | | | This option enables a performance optimization where typical non-blending draws with depth buffer may be rasterized out-of-order (on VI+, multi-SE chips). This optimization can lead to incorrect results when an applications renders multiple objects with the same Z value at the same pixel, so we will never enable it by default. But there may be applications that could benefit from white-listing. Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radeonsi: enable out-of-order rasterization when possible on VI and GFX9 dGPUsNicolai Hähnle2017-09-181-0/+3
| | | | | | | | | This does not take commutative blending into account yet. R600_DEBUG=nooutoforder disables it. Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* amd/common: remove has_ds_bpermute argument from ac_build_ddxyNicolai Hähnle2017-09-181-1/+0
| | | | Reviewed-by: Marek Olšák <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-02 17:14:04 +0000