aboutsummaryrefslogtreecommitdiffstats
path: root/src/gallium/drivers/radeonsi/si_get.c
Commit message (Collapse)AuthorAgeFilesLines
* radeonsi/gfx10: don't expose unimplemented PIPE_CAP_QUERY_SO_OVERFLOWMarek Olšák2019-07-091-1/+3
| | | | | Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Acked-by: Dave Airlie <[email protected]>
* radeonsi: Expose support for 10-bit VP9 decodePratik Vishwakarma2019-07-091-0/+5
| | | | | | | | | | | Fix si_vid_is_format_supported to expose support for 10-bit VP9 decode using P016 format. Without this change, 10-bit decode will be exposed only for HEVC even though newer hardware support 10-bit decode for VP9. Signed-off-by: Pratik Vishwakarma <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeonsi/nir: Use NIR barycentric intrinsicsConnor Abbott2019-07-081-0/+1
| | | | | | | | This is simpler than radv, since the driver_location is already assigned for us. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/gfx10: gfx10 can render up to 8192 layersNicolai Hähnle2019-07-031-0/+4
| | | | Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi: enable jpeg decode for navi10Boyuan Zhang2019-07-031-1/+2
| | | | | Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi: enable encode support for newer HWLeo Liu2019-07-031-5/+3
| | | | | | | Previously it was Raven only allowed to do so Signed-off-by: Leo Liu <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]>
* nir: Add lower_rotate flag and set to true in all driversSagar Ghuge2019-07-011-0/+1
| | | | | | Signed-off-by: Sagar Ghuge <[email protected]> Suggested-by: Matt Turner <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* gallium: Add CAP for opcode DIVGert Wollny2019-06-301-0/+1
| | | | | | | | Not all drivers support TGSI_OPCODE_DIV, so we should have a cap to be able to check this. Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* amd/common: lower bitfield_extract to ubfe/ibfe.Daniel Schürmann2019-06-241-0/+1
| | | | Reviewed-by: Connor Abbott <[email protected]>
* amd/common: lower bitfield_insert to bfm & bitfield_selectDaniel Schürmann2019-06-241-0/+1
| | | | Reviewed-by: Connor Abbott <[email protected]>
* radeonsi: reduce MAX_GEOMETRY_OUTPUT_VERTICESNicolai Hähnle2019-06-171-1/+4
| | | | | | This fixes piglit [email protected]@gs-max-output on gfx9. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac: add radeon_info::is_amdgpu instead of checking drm_major == 3Marek Olšák2019-06-141-2/+2
| | | | | | and clean up Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: Enable NIR's lower_fmod option.Kenneth Graunke2019-06-051-0/+1
| | | | | | | | | | | | | Currently, st/mesa is always calling the GLSL IR lower_instructions() pass with MOD_TO_FLOOR set, so mod operations will be lowered before ever reaching NIR. This enables the same lowering at the NIR level, which will let me shut off the GLSL IR path for NIR-based drivers. The AMD NIR backend also has code to handle fmod, so we could potentially skip this and still be fine. I don't have an opinion on that. Reviewed-by: Marek Olšák <[email protected]>
* gallium: Change PIPE_CAP_TGSI_FS_FBFETCH bool to PIPE_CAP_FBFETCH countKenneth Graunke2019-05-231-1/+1
| | | | | | | | | | | | | | TGSI's FBFETCH instruction currently only supports reading from a single render target, but NIR intrinsics can support multiple render targets. radeonsi can only support fetching from RT 0, but other drivers may be able to support fetching from any render target. To express this, this patch renames PIPE_CAP_TGSI_FS_FBFETCH to simply PIPE_CAP_FBFETCH, and converts it from a boolean "is FBFETCH supported?" to an integer number of render targets which can be fetched. Reviewed-by: Marek Olšák <[email protected]>
* r600+radeonsi: use ctx_query_reset_status on radeonMarek Olšák2019-05-161-2/+1
| | | | This allows a nice cleanup, because the winsys always handles it.
* ac: rename SI-CIK-VI to GFX6-GFX7-GFX8Marek Olšák2019-05-151-1/+1
| | | | | | | | | | | | Acked-by: Dave Airlie <[email protected]> We already use GFX9 and I don't want us to have confusing naming in the driver. GFXn naming is better from the driver perspective, because it's the real version of the gfx portion of the hw. Also, CIK means Bonaire-Kaveri-Kabini, it doesn't mean CI. It shouldn't confuse our SDMA, UVD, VCE etc. code much. Those have nothing to do with GFXn and they have their own version numbers.
* gallium: Redefine the max texture 2d cap from _LEVELS to _SIZE.Eric Anholt2019-05-131-1/+2
| | | | | | | | The _LEVELS assumes that the max is always power of two. For V3D 4.2, we can support up to 7680 non-power-of-two MSAA textures, which will let X11 support dual 4k displays on newer hardware. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: overhaul the vertex fetch fixup mechanismNicolai Hähnle2019-05-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The overall goal is to support unaligned loads from vertex buffers natively on SI. In the unaligned case, we fall back to the general case implementation in ac_build_opencoded_load_format. Since this function is fully general, we will also use it going forward for cases requiring fully manual format conversions of dwords anyway. This requires a different encoding of the fix_fetch array, which will now contain the entire format information if a fixup is required. Having to check the alignment of vertex buffers is awkward. To keep the impact on the fast path minimal, the si_context will keep track of which vertex buffers are (not) at least dword-aligned, while the si_vertex_elements will note which vertex buffers have some (at most dword) alignment requirement. Vertex buffers should be dword-aligned most of the time, which allows a fast early-out in almost all cases. Add the radeonsi_vs_fetch_always_opencode configuration variable for testing purposes. Note that it can only be used reliably on LLVM >= 9, because support for byte and short load is required. v2: - add a missing check to si_bind_vertex_elements Reviewed-by: Marek Olšák <[email protected]>
* nir: nir_shader_compiler_options: drop native_integersChristian Gmeiner2019-05-071-1/+0
| | | | | | | | Driver which do not support native integers should use a lowering pass to go from integers to floats. Signed-off-by: Christian Gmeiner <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* radeonsi: add si_debug_options for convenient adding/removing of optionsNicolai Hähnle2019-04-251-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the definition of radeonsi_clear_db_cache_before_clear there, as well as radeonsi_enable_nir. This removes the AMD_DEBUG=nir option. We currently still have two places for options: the driconf machinery and AMD_DEBUG/R600_DEBUG. If we are to have a single place for options, then the driconf machinery should be preferred since it's more flexible. The only downside of the driconf machinery was that adding new options was quite inconvenient. With this change, a simple boolean option can be added with a single line of code, same as for AMD_DEBUG. One technical limitation of this particular implementation is that while almost all driconf features are available, the translation machinery doesn't pick up the description strings for options added in si_debvug_options. In practice, translations haven't been provided anyway, and this is intended for developer options, so I'm not too worried. It could always be added later if anybody really cares. v2: - use bool instead of uint8_t for options - si_debug_options.inc -> si_debug_options.h Reviewed-by: Marek Olšák <[email protected]>
* gallium: add PIPE_CAP_PREFER_COMPUTE_BLIT_FOR_MULTIMEDIAMarek Olšák2019-04-241-0/+1
|
* gallium: set PIPE_CAP_MAX_FRAMES_IN_FLIGHT to 2 for all driversMarek Olšák2019-04-241-3/+0
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* gallium: replace DRM_CONF_THROTTLE with PIPE_CAP_MAX_FRAMES_IN_FLIGHTMarek Olšák2019-04-231-0/+3
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* ac: add radeon_info::marketing_name, replacing the winsys callbackMarek Olšák2019-04-231-12/+3
| | | | | Tested-by: Dieter Nützel <[email protected]> Acked-by: Nicolai Hähnle <[email protected]>
* nir: optimize gl_SampleMaskIn to gl_HelperInvocation for radeonsi when possibleMarek Olšák2019-04-161-0/+1
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: enable GL_EXT_shader_image_load_formattedMarek Olšák2019-04-151-0/+1
| | | | | | no changes - the driver doesn't use the format Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* simplify LLVM version string printingEric Engestrom2019-04-041-5/+2
| | | | | | | Figure it out once in the build system, then just use that all over the place. Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium: add pipe_grid_info::last_blockMarek Olšák2019-03-151-0/+1
| | | | | | | | | The OpenMAX state tracker will use this. RadeonSI is adapted to use pipe_grid_info::last_block instead of its internal state. Acked-by: Leo Liu <[email protected]>
* radeonsi: Go back to using llvm.pow intrinsic for nir_op_fpowKenneth Graunke2019-02-191-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARB_vertex_program and ARB_fragment_program define 0^0 = 1 (while GLSL leaves it undefined). Performing fpow lowering in NIR would break this behavior, preventing us from using prog_to_nir. According to llvm/lib/Target/AMDGPU/SIInstructions.td, POW_common expands to <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_LEGACY_F32_e32>, which presumably does a zero-wins multiply. Lowering in NIR results in a non-legacy multiply, where: pow(0, 0) = 2^(log2(0) * 0) = 2^(-INF * 0) = 2^(-NaN) = -NaN which isn't the desired result. This reverts: - commit d6b75392067712908bdc372f1007e085439bf9f5 (ac/nir: remove emission of nir_op_fpow) - commit 22430224fec31591432d4a3e65c6f457ba1c1653 (radeonsi/nir: enable lowering of fpow) and prevents a regression in gl-1.0-spot-light with AMD_DEBUG=nir after enabling prog_to_nir in st/mesa later in this series. Reviewed-by: Timothy Arceri <[email protected]>
* gallium: add PIPE_CAP_MAX_VARYINGSKarol Herbst2019-02-071-0/+3
| | | | | | | | | | | | | | | | | Some NVIDIA hardware can accept 128 fragment shader input components, but only have up to 124 varying-interpolated input components. We add a new cap to express this cleanly. For most drivers, this will have the same value as PIPE_SHADER_CAP_MAX_INPUTS for the fragment shader. Fixes KHR-GL45.limits.max_fragment_input_components Signed-off-by: Karol Herbst <[email protected]> [imirkin: rebased, improved docs/commit message] Signed-off-by: Ilia Mirkin <[email protected]> Acked-by: Rob Clark <[email protected]> Acked-by: Eric Anholt <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Cc: 19.0 <[email protected]>
* amd: remove support for LLVM 6.0Samuel Pitoiset2018-12-061-9/+0
| | | | | | | User are encouraged to switch to LLVM 7.0 released in September 2018. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: fix video APIs on Raven2Marek Olšák2018-11-141-3/+6
| | | | | | | | This was missed when I added the new enum. Cc: 18.3 <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* radeonsi: enable vcn jpeg decode for ravenBoyuan Zhang2018-10-231-0/+2
| | | | | | | Enable vcn jpeg decode for raven. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* radeonsi: clamp point size to the limitMarek Olšák2018-10-181-2/+3
| | | | | | | This fixes dEQP-GLES2.functional.rasterization.limits.points. Broken by: ea039f789d9b54e1bd1d644b6a29863ca3500314 Tested-by: Jakob Bornecrantz <[email protected]>
* radeonsi: use higher subpixel precision (QUANT_MODE) for smaller viewportsMarek Olšák2018-10-161-1/+3
|
* gallium: add PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGETMarek Olšák2018-09-071-0/+4
|
* gallium: enable GL_AMD_depth_clamp_separate on r600, radeonsiMarek Olšák2018-09-061-0/+1
|
* nir: Drop the vs_inputs_dual_locations optionJason Ekstrand2018-09-061-1/+0
| | | | | | | | | | | | | It was very inconsistently handled; the only things that made use of it were glsl_to_nir, glspirv, and nir_gather_info. In particular, nir_lower_io completely ignored it so anyone using nir_lower_io on 64-bit vertex attributes was going to be in for a shock. Also, as of the previous commit, it's set by every driver that supports 64-bit vertex attributes. There's no longer any reason to have it be an option so let's just delete it. Reviewed-by: Alejandro Piñeiro <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* radeonsi/nir: Set vs_inputs_dual_locations and let NIR do the remapJason Ekstrand2018-09-061-0/+1
| | | | | | | | | | | | | | | | | We were going out of our way to disable dual-location re-mapping in NIR only to then do the remapping in st_glsl_to_nir.cpp. Presumably, this was so that double_inputs would be correct for the core state tracker. However, now that we've it to gl_program::DualSlotInputs which is unaffected by NIR lowering, we can let NIR lower things for us. The one tricky bit here is that we have to remap the inputs_read bitfield back to the single-slot convention for the gallium state tracker to use. Since radeonsi is the only NIR-capable gallium driver that also supports GL_ARB_vertex_attrib_64bit, we only have to worry about radeonsi when making core gallium state tracker changes. Acked-by: Marek Olšák <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* gallium: add PIPE_CAP_RASTERIZER_SUBPIXEL_BITSMarek Olšák2018-09-061-0/+1
| | | | Reviewed-by: Roland Scheidegger <[email protected]>
* gallium: Add a helper for implementing PIPE_CAP_* default values.Eric Anholt2018-09-041-1/+4
| | | | | | | | | | | | | | | | | | One of the pains of implementing a gallium driver is filling in a million pipe caps you don't know about yet when you're just starting out. One of the pains of working on gallium is copy-and-pasting your new PIPE_CAP into each driver. We can fix both of these by having each driver call into the default helper from their default case, so that both sides can ignore each other until they need to. v2: fix i915g build, revert swr change to avoid breaking scons build (https://travis-ci.org/anholt/mesa/jobs/419739857) v3: Rebase on 3 new gallium caps. Reviewed-by: Marek Olšák <[email protected]> (v1) Cc: Bruce Cherniak <[email protected]> Cc: George Kyriazis <[email protected]> Cc: Kenneth Graunke <[email protected]>
* radeonsi: enable GL 4.5 in compat profileTimothy Arceri2018-08-301-2/+1
| | | | Reviewed-by: Marek Olšák <[email protected]>
* gallium: Split out PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE.Kenneth Graunke2018-08-241-0/+1
| | | | | | | | | | | | | Some hardware can do PIPE_TEX_WRAP_MIRROR_REPEAT but not PIPE_TEX_WRAP_MIRROR_CLAMP and PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER. Drivers for such hardware would like to advertise support for ARB_texture_mirror_clamp_to_edge but not EXT_texture_mirror_clamp. This commit adds a new PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE bit, changes the extension enable to be based on that, and enables it in all upstream drivers which supported PIPE_CAP_TEXTURE_MIRROR_CLAMP (so they continue supporting this mode).
* radeonsi: increase the maximum UBO size to 2 GBMarek Olšák2018-08-231-1/+1
| | | | | | | | | Same as the closed driver. This causes a failure in GL45-CTS.compute_shader.max, which has a trivial bug. Tested-by: Dieter Nützel <[email protected]>
* radeonsi: bump MAX_GS_INVOCATIONSMarek Olšák2018-08-231-1/+3
| | | | | | same as the closed driver Tested-by: Dieter Nützel <[email protected]>
* gallium: add PIPE_CAP_MAX_SHADER_BUFFER_SIZEMarek Olšák2018-08-231-0/+1
| | | | Tested-by: Dieter Nützel <[email protected]>
* gallium: add PIPE_CAP_MAX_GS_INVOCATIONSMarek Olšák2018-08-231-0/+2
| | | | Tested-by: Dieter Nützel <[email protected]>
* radeonsi: use radeon_info::nameMarek Olšák2018-08-141-38/+11
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* radeonsi: implement EXT_window_rectanglesMarek Olšák2018-08-141-1/+1
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* gallium: add PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTSMarek Olšák2018-07-311-0/+2
| | | | Tested-by: Dieter Nützel <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-03 00:31:23 +0000