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* radeonsi: Apply si_* file naming scheme.Andreas Hartmetz2014-01-141-263/+0
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: fix binding the dummy pixel shaderMarek Olšák2013-12-121-1/+1
| | | | | | This fixes valgrind errors in glxinfo. Reviewed-by: Michel Dänzer <[email protected]>
* r600g,radeonsi: consolidate buffer code, add handling of DISCARD_RANGE for SIMarek Olšák2013-12-121-5/+0
| | | | | | | | This adds 2 optimizations for radeonsi: - handling of DISCARD_RANGE - mapping an uninitialized buffer range is automatically UNSYNCHRONIZED Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: bind a dummy constant buffer in place of NULL buffersMarek Olšák2013-11-041-0/+1
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* r600g,radeonsi: use fences provided by the winsysMarek Olšák2013-10-251-26/+0
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* r600g,radeonsi: share r600_texture.cMarek Olšák2013-09-291-10/+0
| | | | | | | | | The function r600_choose_tiling is new and needs a review. The only change in functionality is that it enables 2D tiling for compressed textures on SI. It was probably accidentally turned off. v2: don't make scanout buffers linear
* r600g,radeonsi: consolidate tiling_info initializationMarek Olšák2013-09-291-2/+0
| | | | and the util_format_s3tc_init calls too.
* radeonsi: move radeonsi-specific functions out of r600_texture.cMarek Olšák2013-09-291-3/+0
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* r600g,radeonsi: remove unused codeMarek Olšák2013-09-291-1/+0
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* radeonsi: bind streamout buffers to VGT and the vertex shaderMarek Olšák2013-09-131-0/+2
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: initialize the first CS like any otherMarek Olšák2013-09-131-0/+2
| | | | | | | | | So that the "init" state is always emitted first and not later in draw_vbo. This fixes streamout where the "init" state, which disables streamout, was emitted in draw_vbo after streamout was enabled. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: integrate shared streamout stateMarek Olšák2013-09-131-8/+1
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: simplify and improve flushingMarek Olšák2013-08-311-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This mimics r600g. The R600_CONTEXT_xxx flags are added to rctx->b.flags and si_emit_cache_flush emits the packets. That's it. The shared radeon code tells us when the streamout cache should be flushed, so we have to check the flags anyway. There is a new atom "cache_flush", because caches must be flushed *after* resource descriptors are changed in memory. Functional changes: * Write caches are flushed at the end of CS and read caches are flushed at its beginning. * Sampler view states are removed from si_state, they only held the flush flags. * Everytime a shader is changed, the I cache is flushed. Is this needed? Due to a hw bug, this also flushes the K cache. * The WRITE_DATA packet is changed to use TC, which fixes a rendering issue in openarena. I'm not sure how TC interacts with CP DMA, but for now it seems to work better than any other solution I tried. (BTW CIK allows us to use TC for CP DMA.) * Flush the K cache instead of the texture cache when updating resource descriptors (due to a hw bug, this also flushes the I cache). I think the K cache flush is correct here, but I'm not sure if the texture cache should be flushed too (probably not considering we use TC for WRITE_DATA, but we don't use TC for CP DMA). * The number of resource contexts is decreased to 16. With all of these cache changes, 4 doesn't work, but 8 works, which suggests I'm actually doing the right thing here and the pipeline isn't drained during flushes. Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]> Tested-by: Tom Stellard <[email protected]>
* radeonsi: convert constant buffers to si_descriptorsMarek Olšák2013-08-311-8/+2
| | | | | | | | | | | | | | | There is a new "class" si_buffer_resources, which should be good enough for implementing any kind of buffer bindings (constant buffers, vertex buffers, streamout buffers, shader storage buffers, etc.) I don't even keep a copy of pipe_constant_buffer - we don't need it. The main motivation behind this is to have a well-tested infrastrusture for setting up streamout buffers. Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]> Tested-by: Tom Stellard <[email protected]>
* radeonsi: use r600_common_context, r600_common_screen, r600_resourceMarek Olšák2013-08-311-29/+13
| | | | | | | | | Also r600_hw_context_priv.h and si_state_streamout.c are removed, because they are no longer needed. Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]> Tested-by: Tom Stellard <[email protected]>
* r600g,radeonsi: remove unused variablesMarek Olšák2013-08-311-5/+0
| | | | | | Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]> Tested-by: Tom Stellard <[email protected]>
* radeonsi: Do not suspend timer queriesNiels Ole Salscheider2013-08-301-2/+2
| | | | | Signed-off-by: Niels Ole Salscheider <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* vl: rename pipe_video_decoder to pipe_video_codecChristian König2013-08-191-2/+2
| | | | Signed-off-by: Christian König <[email protected]>
* vl: use a template for create_video_decoderChristian König2013-08-191-5/+1
| | | | Signed-off-by: Christian König <[email protected]>
* radeonsi: port texture improvements from r600gMarek Olšák2013-08-171-5/+6
| | | | | | | | | | | | | | This started as an attempt to add support for MSAA texture transfers and MSAA depth-stencil decompression for the DB->CB copy path. It has gotten a bit out of control, but it's for the greater good. Some changes do not make much sense, they are there just to make it look like the other driver. With a few cosmetic modifications, r600_texture.c can be shared with a symlink. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: add FMASK texture binding slots and resource setup (v2)Marek Olšák2013-08-171-0/+1
| | | | | | v2: bind FMASK textures to shader resource slots 16..31 Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: implement FMASK decompression for MSAA texturingMarek Olšák2013-08-171-0/+5
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: implement MSAA colorbuffer compression for renderingMarek Olšák2013-08-171-0/+2
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: implement GL_SAMPLE_ALPHA_TO_ONEMarek Olšák2013-08-171-0/+1
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: implement uncompressed MSAA rendering and color resolvingMarek Olšák2013-08-171-0/+2
| | | | | | | This is basic MSAA support which should work with most apps. Some features are missing, those will be implemented by other commits. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: add flexible shader descriptor management and use it for sampler viewsMarek Olšák2013-08-171-6/+13
| | | | | | | | | | | | | | | | | | | | | | | It moves all sampler view descriptors to a buffer. It supports partial resource updates and it can also unbind resources (required for FMASK texturing). The buffer contains all sampler view descriptors for one shader stage, represented as an array. On top of that, there are N arrays in the buffer, which are used to emulate context registers as implemented by the previous ASICs (each array is a context). This uses the RCU synchronization approach to avoid read-after-write hazards as discussed in the thread: "radeonsi: add FMASK texture binding slots and resource setup" CP DMA is used to clear the descriptors at context initialization and to copy the descriptors from one context to the next. v2: - use PKT3_DMA_DATA on CIK (I'll test CIK later) - turn the bool CP DMA parameters into self-explanatory flags - add a nice simple API for packet emission to radeon_winsys.h - use 256 contexts, 128 causes texture corruption in openarena
* radeonsi: rename r600_resource_texture to r600_textureMarek Olšák2013-08-151-2/+2
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* gallium: add condition parameter to render_conditionRoland Scheidegger2013-06-181-0/+2
| | | | | | | | | | | | | For conditional rendering this makes it possible to skip rendering if either the predicate is true or false, as supported by d3d10 (in fact previously it was sort of implied skip rendering if predicate is false for occlusion predicate, and true for so_overflow predicate). There's no cap bit for this as presumably all drivers could do it trivially (but this patch does not implement it for the drivers using true hw predicates, nvxx, r600, radeonsi, no change is expected for OpenGL functionality). Reviewed-by: Jose Fonseca <[email protected]>
* radeonsi: Make border colour state handling safe for integer texturesMichel Dänzer2013-05-281-1/+1
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* radeonsi: Handle TGSI_SEMANTIC_CLIPVERTEXMichel Dänzer2013-05-211-1/+0
| | | | | | 17 more little piglits. NOTE: This is a candidate for the 9.1 branch.
* radeonsi: Initial support for multiple constant buffersMichel Dänzer2013-05-211-0/+8
| | | | | | | Just enough to support an additional internal constant buffer for the user clip planes. NOTE: This is a candidate for the 9.1 branch.
* radeonsi: Fix handling of TGSI_SEMANTIC_PSIZEMichel Dänzer2013-05-211-1/+0
| | | | | | Two more little piglits. NOTE: This is a candidate for the 9.1 branch.
* radeon/uvd: add UVD implementation v5Christian König2013-04-111-0/+11
| | | | | | | | | | | | | | Just everything you need for UVD with r600g and radeonsi. v2: move UVD code to radeon subdir, clean up build system additions, remove an unused SI function, disable tiling on SI for now. v3: some minor indentation fix and rebased v4: dpb size calculation fixed v5: implement proper fall-back in case the kernel doesn't support UVD, based on patches from Andreas Boll but cleaned up a bit more. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: Add compute support v3Tom Stellard2013-04-051-0/+10
| | | | | | | | | | | v2: - Only dump shaders when env variable is set. v3: - Don't emit VGT registers Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Michel Dänzer <[email protected]
* gallium: PIPE_COMPUTE_CAP_IR_TARGET - allow drivers to specify a processor v2Tom Stellard2013-04-051-0/+1
| | | | | | | | | | | | This target string now contains four values instead of three. The old processor field (which was really being interpreted as arch) has been split into two fields: processor and arch. This allows drivers to pass a more a more detailed description of the hardware to compiler frontends. v2: - Adapt to libclc changes Reviewed-by: Francisco Jerez <[email protected]>
* radeonsi: add cs tracing v3Jerome Glisse2013-03-271-0/+12
| | | | | | | | | | | Same as on r600, trace cs execution by writting cs offset after each states, this allow to pin point lockup inside command stream and narrow down the scope of lockup investigation. v2: Use WRITE_DATA packet instead of WRITE_MEM v3: Remove useless nop packet Signed-off-by: Jerome Glisse <[email protected]>
* gallium/util: add helper util_max_layer from r600gMarek Olšák2013-02-261-16/+0
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* radeonsi: add assertions to prevent creation of invalid surfacesMarek Olšák2013-02-201-0/+16
| | | | | | | | [ Cherry-picked from r600g commit ef11ed61a0414d0405c3faf7f48fa3f1d083f82e ] NOTE: This is a candidate for the 9.1 branch. Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: More assorted depth/stencil changes ported from r600g.Marek Olšák2013-01-211-4/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [ Squashed port of the following r600g commits: - Michel Dänzer ] commit 428e37c2da420f7dc14a2ea265f2387270f9bee1 Author: Marek Olšák <[email protected]> Date: Tue Oct 2 22:02:54 2012 +0200 r600g: add in-place DB decompression and texturing with DB tiling The decompression is done in-place and only the compressed tiles are decompressed. Note: R6xx-R7xx can do that only with Z16 and Z32F. The texture unit is programmed to use non-displayable tiling and depth ordering of samples, so that it can fetch the texture in the native DB format. The latest version of the libdrm surface allocator is required for stencil texturing to work. The old one didn't create the mipmap tree correctly. We need a separate mipmap tree for stencil, because the stencil mipmap offsets are not really depth offsets/4. There are still some known bugs, but this should save some memory and it also improves performance a little bit in Lightsmark (especially with low resolutions; tested with Radeon HD 5000). The DB->CB copy is still used for transfers. commit e2f623f1d6da9bc987582ff68d0471061ae44030 Author: Marek Olšák <[email protected]> Date: Sat Jul 28 13:55:59 2012 +0200 r600g: don't decompress depth or stencil if there isn't any commit 43e226b6efb77db2247741cc2057d9625a2cfa05 Author: Marek Olšák <[email protected]> Date: Wed Jul 18 00:32:50 2012 +0200 r600g: optimize uploading depth textures Make it only copy the portion of a depth texture being uploaded and not the whole 2D layer. There is also a little code cleanup. commit b242adbe5cfa165b252064a1ea36f802d8251ef1 Author: Marek Olšák <[email protected]> Date: Wed Jul 18 00:17:46 2012 +0200 r600g: remove needless wrapper r600_texture_depth_flush commit 611dd529425281d73f1f0ad2000362d4a5525a25 Author: Marek Olšák <[email protected]> Date: Wed Jul 18 00:05:14 2012 +0200 r600g: init_flushed_depth_texture should be able to report errors commit 80755ff56317446a8c89e611edc1fdf320d6779b Author: Marek Olšák <[email protected]> Date: Sat Jul 14 17:06:27 2012 +0200 r600g: properly track which textures are depth This fixes the issue with have_depth_texture never being set to false. commit fe1fd675565231b49d3ac53d0b4bec39d8bc6781 Author: Marek Olšák <[email protected]> Date: Sun Jul 8 03:10:37 2012 +0200 r600g: don't flush depth textures set as colorbuffers The only case a depth buffer can be set as a color buffer is when flushing. That wasn't always the case, but now this code isn't required anymore. commit 5a17d8318ec2c20bf86275044dc8f715105a88e7 Author: Marek Olšák <[email protected]> Date: Sun Jul 8 02:14:18 2012 +0200 r600g: flush depth textures bound to vertex shaders This was missing/broken. There are also minor code cleanups. commit dee58f94af833906863b0ff2955b20f3ab407e63 Author: Marek Olšák <[email protected]> Date: Sun Jul 8 01:54:24 2012 +0200 r600g: do fine-grained depth texture flushing - maintain a mask of which mipmap levels are dirty (instead of one big flag) - only flush what was requested at a given point and not the whole resource (most often only one level and one layer has to be flushed) Signed-off-by: Michel Dänzer <[email protected]>
* radeonsi: improve flushed depth texture handlingVadim Girlin2013-01-211-1/+3
| | | | | | | | | | | | | Use r600_resource_texture::flished_depth_texture for GPU access, and allocate it in the VRAM. For transfers we'll allocate texture in the GTT and store it in the r600_transfer::staging. Improves performance when flushed depth texture is frequently used by the GPU, e.g. in Lightsmark [ Ported from r600g commit 37708479608af877986b76302a9c92611d1e23d0 ] Signed-off-by: Michel Dänzer <[email protected]>
* radeonsi: Assorted depth/stencil changes ported from r600g.Marek Olšák2013-01-211-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | [ Squashed port of the following r600g commits: - Michel Dänzer ] commit c1e8c845ea9c6f843cc5bba5974668c007799bbc Author: Marek Olšák <[email protected]> Date: Sat Jul 7 19:10:00 2012 +0200 r600g: inline r600_hw_copy_region commit 4891c5dc64ccd8cf2bf8a8550ae23e1a61806a7d Author: Marek Olšák <[email protected]> Date: Mon Jun 25 22:53:21 2012 +0200 r600g: inline r600_blit_push_depth and use resource_copy_region We are going to have a separate resource for depth texturing and transfers and this is just a transfer thing. commit da98bb6fc105e1a2f688a1713ca9e50f0ac8fbed Author: Marek Olšák <[email protected]> Date: Mon Jun 25 12:45:32 2012 +0200 r600g: split flushed depth texture creation and flushing Signed-off-by: Michel Dänzer <[email protected]>
* radeonsi: Set SPI_SHADER_COL_FORMAT to what the pixel shader actually exports.Michel Dänzer2013-01-171-1/+0
| | | | | | | | | Instead of deriving it from the colour buffer formats only. Fixes a number of piglit tests which export depth from the pixel shader. Reviewed-by: Christian König <[email protected]> Signed-off-by: Michel Dänzer <[email protected]>
* winsys/radeon: don't use BIND flags, add a flag for the cache bufmgr insteadMarek Olšák2012-12-121-1/+1
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* radeonsi: Fix sampler views for depth textures.Michel Dänzer2012-11-281-0/+1
| | | | | | | Consistently reference the flushed depth texture in the sampler view, not the original one. Signed-off-by: Michel Dänzer <[email protected]>
* radeonsi: Implement alpha testing in pixel shader.Michel Dänzer2012-11-121-2/+0
| | | | Signed-off-by: Michel Dänzer <[email protected]>
* radeonsi: start reworking inferred state handlingChristian König2012-09-261-1/+0
| | | | | | | | | | | Instead of tracking the inferred state changes separately just check if queued and emitted states are the same. This patch just reworks the update of the SPI map between vs and ps, but there are probably more cases like this. Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: Texture border colour fixes.Michel Dänzer2012-09-111-0/+3
| | | | | | | | | | * Handle arbitrary border colours. * Use correct packing format for detecting special border colours. Fixes piglit tex-border-1 and probably many other tests using border colours. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: adjust PIPE_SHADER_CAP_MAX_CONSTSChristian König2012-09-041-3/+0
| | | | | | | So it matches what we really can do. Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: Use FP16 shader export format when necessary / possible.Michel Dänzer2012-08-271-1/+2
| | | | | | | | | Fixes piglit fbo-blending-formats. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: Maintain cache of pixel shader variants according to contxt state.Michel Dänzer2012-08-271-2/+2
| | | | | | | | | Mostly inspired by r600g commit 4acf71f01ea1edb253cd38cc059d4af1a2a40bf4 ('r600g: cache shader variants instead of rebuilding v3'). Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
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