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* radeonsi: Handle additional PIPE_COMPUTE_CAP_*Niels Ole Salscheider2013-08-231-1/+14
| | | | | | | | | | | This patch adds support for: PIPE_COMPUTE_CAP_MAX_INPUT_SIZE PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE Return the values reported by the closed source driver for now. Signed-off-by: Niels Ole Salscheider <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeonsi: copy r600_get_timestampNiels Ole Salscheider2013-08-231-0/+9
| | | | | Signed-off-by: Niels Ole Salscheider <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Implement PIPE_QUERY_TIMESTAMPNiels Ole Salscheider2013-08-231-1/+1
| | | | | Signed-off-by: Niels Ole Salscheider <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* vl: add entrypoint to get_video_paramChristian König2013-08-191-1/+2
| | | | Signed-off-by: Christian König <[email protected]>
* vl: rename pipe_video_decoder to pipe_video_codecChristian König2013-08-191-2/+2
| | | | Signed-off-by: Christian König <[email protected]>
* radeonsi: fix feature support reportingMarek Olšák2013-08-171-0/+1
| | | | broken by 21d9a1b5ef51ce449e9a82641d0d605c5448b41c
* radeonsi: require LLVM 3.4 for MSAAMarek Olšák2013-08-171-1/+2
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* radeonsi: port texture improvements from r600gMarek Olšák2013-08-171-3/+5
| | | | | | | | | | | | | | This started as an attempt to add support for MSAA texture transfers and MSAA depth-stencil decompression for the DB->CB copy path. It has gotten a bit out of control, but it's for the greater good. Some changes do not make much sense, they are there just to make it look like the other driver. With a few cosmetic modifications, r600_texture.c can be shared with a symlink. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: implement FMASK decompression for MSAA texturingMarek Olšák2013-08-171-0/+1
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: implement uncompressed MSAA texturingMarek Olšák2013-08-171-1/+2
| | | | | | | This is glBlitFramebuffer support for MSAA surfaces as required by GL 3.0 and texturing as required by GL 3.2 and GL_ARB_texture_multisample. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: implement uncompressed MSAA rendering and color resolvingMarek Olšák2013-08-171-0/+1
| | | | | | | This is basic MSAA support which should work with most apps. Some features are missing, those will be implemented by other commits. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: add flexible shader descriptor management and use it for sampler viewsMarek Olšák2013-08-171-1/+6
| | | | | | | | | | | | | | | | | | | | | | | It moves all sampler view descriptors to a buffer. It supports partial resource updates and it can also unbind resources (required for FMASK texturing). The buffer contains all sampler view descriptors for one shader stage, represented as an array. On top of that, there are N arrays in the buffer, which are used to emulate context registers as implemented by the previous ASICs (each array is a context). This uses the RCU synchronization approach to avoid read-after-write hazards as discussed in the thread: "radeonsi: add FMASK texture binding slots and resource setup" CP DMA is used to clear the descriptors at context initialization and to copy the descriptors from one context to the next. v2: - use PKT3_DMA_DATA on CIK (I'll test CIK later) - turn the bool CP DMA parameters into self-explanatory flags - add a nice simple API for packet emission to radeon_winsys.h - use 256 contexts, 128 causes texture corruption in openarena
* radeonsi: unduplicate code in create_contextMarek Olšák2013-08-151-6/+0
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* vl: Add support for max level query v2Rico Schüller2013-08-141-0/+2
| | | | | | | | | This patch adds the level query support to the video decoders and uses some more reasonable defaults. v2: (ck) add commit message Reviewed-by: Christian König <[email protected]>
* gallium: Add PIPE_CAP_ENDIANNESSTom Stellard2013-07-221-0/+2
| | | | | | Cc: [email protected] [ Francisco Jerez: Fix "PIPE_ENDIAN_SMALL" in the documentation, define PIPE_ENDIAN_NATIVE. ]
* mesa,glsl,gallium: remove GLSLSkipStrictMaxVaryingLimitCheck and dependenciesMarek Olšák2013-07-021-1/+0
| | | | | | Not needed with do_dead_builtin_varyings. Reviewed-by: Ian Romanick <[email protected]>
* radeonsi: add llvm processor names for CIKAlex Deucher2013-06-281-0/+3
| | | | | | Requires updated llvm. Signed-off-by: Alex Deucher <[email protected]>
* radeonsi: initial support for CIK chipsAlex Deucher2013-06-281-1/+13
| | | | | | | Add the infrastructure to differentiate them. Just treat them like SI for now. Signed-off-by: Alex Deucher <[email protected]>
* radeonsi: rename SI chip class from TAHITI to SIAlex Deucher2013-06-281-2/+2
| | | | | | Covers the entire family. Signed-off-by: Alex Deucher <[email protected]>
* gallium: add condition parameter to render_conditionRoland Scheidegger2013-06-181-2/+4
| | | | | | | | | | | | | For conditional rendering this makes it possible to skip rendering if either the predicate is true or false, as supported by d3d10 (in fact previously it was sort of implied skip rendering if predicate is false for occlusion predicate, and true for so_overflow predicate). There's no cap bit for this as presumably all drivers could do it trivially (but this patch does not implement it for the drivers using true hw predicates, nvxx, r600, radeonsi, no change is expected for OpenGL functionality). Reviewed-by: Jose Fonseca <[email protected]>
* radeonsi/compute: Add missing PIPE_COMPUTE capsTom Stellard2013-06-031-0/+16
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* radeonsi: Enable GLSL 1.30Michel Dänzer2013-05-281-1/+1
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* radeonsi: update r600_get_llvm_processor_name for hainanAlex Deucher2013-05-141-0/+1
| | | | | Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: add support for hainan chipsAlex Deucher2013-05-141-0/+1
| | | | | | | Note: this is a candidate for the 9.1 branch Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* gallium: add PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE for GLMarek Olšák2013-05-111-0/+1
| | | | | | v2: fix typo 65535 -> 65536 Reviewed-by: Brian Paul <[email protected]>
* gallium: fix type of flags in pipe_context::flush()Chia-I Wu2013-05-041-1/+1
| | | | | | | | | | | | | | | | It should be unsigned, not enum pipe_flush_flags. Fixed a build error: src/gallium/state_trackers/egl/android/native_android.cpp:426:29: error: invalid conversion from 'int' to 'pipe_flush_flags' [-fpermissive] v2: replace all occurrences of enum pipe_flush_flags by unsigned Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Marek Olšák <[email protected]> [olv: document the parameter now that the type is unsigned]
* winsys/radeon: consolidate tracing into winsys v2Jerome Glisse2013-04-251-1/+1
| | | | | | | | | | | | This move the tracing timeout and printing into winsys and add an debug environement variable for it (R600_DEBUG=trace_cs). Lot of file touched because of winsys API changes. v2: Do not write lockup file if ib uniq id does not match last one Signed-off-by: Jerome Glisse <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* st/mesa: optionally apply texture swizzle to border color v2Christoph Bumiller2013-04-181-0/+1
| | | | | | | | | | | | This is the only sane solution for nv50 and nvc0 (really, trust me), but since on other hardware the border colour is tightly coupled with texture state they'd have to undo the swizzle, so I've added a cap. The dependency of update_sampler on the texture updates was introduced to avoid doing the apply_depthmode to the swizzle twice. v2: Moved swizzling helper to u_format.c, extended the CAP to provide more accurate information.
* radeon/uvd: add UVD implementation v5Christian König2013-04-111-4/+17
| | | | | | | | | | | | | | Just everything you need for UVD with r600g and radeonsi. v2: move UVD code to radeon subdir, clean up build system additions, remove an unused SI function, disable tiling on SI for now. v3: some minor indentation fix and rebased v4: dpb size calculation fixed v5: implement proper fall-back in case the kernel doesn't support UVD, based on patches from Andreas Boll but cleaned up a bit more. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: Add compute support v3Tom Stellard2013-04-051-1/+60
| | | | | | | | | | | v2: - Only dump shaders when env variable is set. v3: - Don't emit VGT registers Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Michel Dänzer <[email protected]
* gallium: PIPE_COMPUTE_CAP_IR_TARGET - allow drivers to specify a processor v2Tom Stellard2013-04-051-0/+11
| | | | | | | | | | | | This target string now contains four values instead of three. The old processor field (which was really being interpreted as arch) has been split into two fields: processor and arch. This allows drivers to pass a more a more detailed description of the hardware to compiler frontends. v2: - Adapt to libclc changes Reviewed-by: Francisco Jerez <[email protected]>
* gallium: add PIPE_CAP_QUERY_PIPELINE_STATISTICSChristoph Bumiller2013-04-031-0/+1
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: add instanceid supportChristian König2013-04-021-1/+1
| | | | | | Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Tested-by: Michel Dänzer <[email protected]>
* radeonsi: add cs tracing v3Jerome Glisse2013-03-271-0/+22
| | | | | | | | | | | Same as on r600, trace cs execution by writting cs offset after each states, this allow to pin point lockup inside command stream and narrow down the scope of lockup investigation. v2: Use WRITE_DATA packet instead of WRITE_MEM v3: Remove useless nop packet Signed-off-by: Jerome Glisse <[email protected]>
* gallium,st/mesa: don't use blit-based transfers with software rasterizersMarek Olšák2013-03-231-0/+1
| | | | | | | | | The blit-based paths for TexImage, GetTexImage, and ReadPixels aren't very fast with software rasterizer. Now Gallium drivers have the ability to turn them off. Reviewed-by: Brian Paul <[email protected]> Tested-by: Brian Paul <[email protected]>
* gallium: add TGSI_SEMANTIC_TEXCOORD,PCOORD v3Christoph Bumiller2013-03-201-0/+2
| | | | | | | | | | | | | | | This makes it possible to identify gl_TexCoord and gl_PointCoord for drivers where sprite coordinate replacement is restricted. The new PIPE_CAP_TGSI_TEXCOORD decides whether these varyings should be hidden behind the GENERIC semantic or not. With this patch only nvc0 and nv30 will request that they be used. v2: introduce a CAP so other drivers don't have to bother with the new semantic v3: adapt to introduction gl_varying_slot enum
* radeonsi: enable indirect adressingChristian König2013-03-191-1/+1
| | | | | | | Fixing 16 piglit tests. Signed-off-by: Christian König <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeonsi: remove constant index limitation v3Christian König2013-02-121-1/+1
| | | | | | | | | | With the llvm patches, fixing 14 piglit tests in total. v2: increase the const limit v3: document the const limit Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: add support for Oland chipsAlex Deucher2013-02-041-0/+1
| | | | | | Signed-off-by: Alex Deucher <[email protected]> Note: this is a candidate for the 9.1 branch
* gallium/drivers: handle PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED queryBrian Paul2013-02-041-0/+2
| | | | Initially, only softpipe/llvmpipe support SQRT.
* radeonsi: Enable texture arrays.Michel Dänzer2013-02-041-1/+1
| | | | | | 28/30 piglit tests pass. NOTE: This is a candidate for the 9.1 branch.
* gallium: handle unhandled PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENTAndreas Boll2013-02-041-0/+1
| | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60098 Signed-off-by: Brian Paul <[email protected]>
* radeonsi: port some of get_shader_param changes from r600gMarek Olšák2013-02-011-6/+2
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeon/winsys: add dma ring support to winsys v3Jerome Glisse2013-01-281-1/+1
| | | | | | | | | | | | | | | | | | | | Add ring support, you can create a cs for each ring. DMA ring is bit special regarding relocation as you must emit as much relocation as there is use of the buffer. v2: - Improved comment on relocation changes - Use a single thread to queue cs submittion this simplify driver code while not impacting performances. Rational for this is that you have to wait for all previous submission to have completed so there was never a case while we could have 2 different thread submitting a command stream at the same time. This code just consolidate submission into one single thread per winsys. v3: - Do not use semaphore for empty queue signaling, instead use cond var. This is because it's tricky to maintain an even number of call to semaphore wait and semaphore signal (the number of cs in the stack would for instance make that number vary). Signed-off-by: Jerome Glisse <[email protected]>
* radeonsi: More assorted depth/stencil changes ported from r600g.Marek Olšák2013-01-211-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [ Squashed port of the following r600g commits: - Michel Dänzer ] commit 428e37c2da420f7dc14a2ea265f2387270f9bee1 Author: Marek Olšák <[email protected]> Date: Tue Oct 2 22:02:54 2012 +0200 r600g: add in-place DB decompression and texturing with DB tiling The decompression is done in-place and only the compressed tiles are decompressed. Note: R6xx-R7xx can do that only with Z16 and Z32F. The texture unit is programmed to use non-displayable tiling and depth ordering of samples, so that it can fetch the texture in the native DB format. The latest version of the libdrm surface allocator is required for stencil texturing to work. The old one didn't create the mipmap tree correctly. We need a separate mipmap tree for stencil, because the stencil mipmap offsets are not really depth offsets/4. There are still some known bugs, but this should save some memory and it also improves performance a little bit in Lightsmark (especially with low resolutions; tested with Radeon HD 5000). The DB->CB copy is still used for transfers. commit e2f623f1d6da9bc987582ff68d0471061ae44030 Author: Marek Olšák <[email protected]> Date: Sat Jul 28 13:55:59 2012 +0200 r600g: don't decompress depth or stencil if there isn't any commit 43e226b6efb77db2247741cc2057d9625a2cfa05 Author: Marek Olšák <[email protected]> Date: Wed Jul 18 00:32:50 2012 +0200 r600g: optimize uploading depth textures Make it only copy the portion of a depth texture being uploaded and not the whole 2D layer. There is also a little code cleanup. commit b242adbe5cfa165b252064a1ea36f802d8251ef1 Author: Marek Olšák <[email protected]> Date: Wed Jul 18 00:17:46 2012 +0200 r600g: remove needless wrapper r600_texture_depth_flush commit 611dd529425281d73f1f0ad2000362d4a5525a25 Author: Marek Olšák <[email protected]> Date: Wed Jul 18 00:05:14 2012 +0200 r600g: init_flushed_depth_texture should be able to report errors commit 80755ff56317446a8c89e611edc1fdf320d6779b Author: Marek Olšák <[email protected]> Date: Sat Jul 14 17:06:27 2012 +0200 r600g: properly track which textures are depth This fixes the issue with have_depth_texture never being set to false. commit fe1fd675565231b49d3ac53d0b4bec39d8bc6781 Author: Marek Olšák <[email protected]> Date: Sun Jul 8 03:10:37 2012 +0200 r600g: don't flush depth textures set as colorbuffers The only case a depth buffer can be set as a color buffer is when flushing. That wasn't always the case, but now this code isn't required anymore. commit 5a17d8318ec2c20bf86275044dc8f715105a88e7 Author: Marek Olšák <[email protected]> Date: Sun Jul 8 02:14:18 2012 +0200 r600g: flush depth textures bound to vertex shaders This was missing/broken. There are also minor code cleanups. commit dee58f94af833906863b0ff2955b20f3ab407e63 Author: Marek Olšák <[email protected]> Date: Sun Jul 8 01:54:24 2012 +0200 r600g: do fine-grained depth texture flushing - maintain a mask of which mipmap levels are dirty (instead of one big flag) - only flush what was requested at a given point and not the whole resource (most often only one level and one layer has to be flushed) Signed-off-by: Michel Dänzer <[email protected]>
* gallium: remove PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATEMarek Olšák2013-01-151-1/+0
| | | | Reviewed-by: Brian Paul <[email protected]>
* gallium/radeon: send the END_OF_FRAME flag to the DRMMarek Olšák2013-01-041-1/+2
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* gallium: extend pipe_context::flush for it to accept an END_OF_FRAME flagMarek Olšák2013-01-041-1/+2
| | | | | | | | | | | | | | | | | Usage with pipe_context: pipe->flush(pipe, NULL, PIPE_FLUSH_END_OF_FRAME); Usage with st_context_iface: st->flush(st, ST_FLUSH_END_OF_FRAME, NULL); The flag is only a hint for drivers. Radeon will use it for buffer eviction heuristics in the kernel (e.g. for queries like how many frames have passed since a buffer was used). The flag is currently only generated by st/dri on SwapBuffers. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Stéphane Marchesin <[email protected]>
* radeonsi: fix int->bool conversion in fence_signalledMarek Olšák2013-01-041-1/+1
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* gallium: s/PIPE_CAP_TIMER_QUERY/PIPE_CAP_QUERY_TIME_ELAPSED/José Fonseca2012-12-201-1/+1
| | | | | | | | To better reflect what it is being advertised. Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Brian Paul <[email protected]>
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