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* radeon/llvm: Remove AMDIL ADD instructionsTom Stellard2012-05-246-179/+4
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* radeon/llvm: Remove AMDIL binary instrutions (OR, AND, XOR, NOT)Tom Stellard2012-05-248-422/+8
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* radeon/llvm: Remove AMDILMachinePeephole passTom Stellard2012-05-244-177/+0
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* radeon/llvm: Remove AMDIL CMP instructions and associated lowering codeTom Stellard2012-05-243-661/+22
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* radeon/llvm: Remove AMDIL ROUND_NEAREST instructionTom Stellard2012-05-244-6/+6
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* radeon/llvm: Remove AMDIL ROUND_POSINF instructionTom Stellard2012-05-244-6/+10
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* radeon/llvm: Add custom SDNode for FRACTTom Stellard2012-05-246-6/+10
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* radeon/llvm: Use -1 as true value for SET* integer instructionsTom Stellard2012-05-243-32/+28
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* radeon/llvm: Handle SETGE_INT, SETGE_UINT, and SETGT_UINT opcodesTom Stellard2012-05-241-0/+6
| | | | | Support for these was inadvertently dropped in commit cee23ab246f22210b3063cdc47bdb45b3d943526
* radeon/llvm: Avoid error with SI in EmitInstrWithCustomInserter()Tom Stellard2012-05-241-0/+1
| | | | | | We need to return immediately after inserting instructions that require S_WAITCNT so that the parent class' custom inserter won't try to insert them again.
* radeon/llvm: Handle selectcc DAG nodeTom Stellard2012-05-207-54/+350
| | | | | R600 can now select instructions from the selectcc DAG node, which is typically lowered to one of the SET* instructions.
* radeon/llvm: Fix segfault while lowering lrp intrinsicTom Stellard2012-05-171-2/+3
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* radeon/llvm: Add DAG nodes for MIN instructionsTom Stellard2012-05-176-14/+38
| | | | Also, remove the AMDIL MIN* instruction defs.
* radeon/llvm: Lower lrp intrinsic during ISelTom Stellard2012-05-173-7/+19
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* radeon/llvm: Remove AMDIL MAD instruction defsTom Stellard2012-05-176-7/+14
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* radeon/llvm: Remove AMDIL MUL_IEEE* instructionsTom Stellard2012-05-173-7/+3
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* radeon/llvm: Expand fsub during ISelTom Stellard2012-05-172-11/+2
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* radeon/llvm: Remove AMDIL floating-point ADD instruction defsTom Stellard2012-05-175-8/+9
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* radeon/llvm: Remove AMDIL CMOVLOG* instruction defsTom Stellard2012-05-174-26/+6
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* radeon/llvm: Move lowering of ABS_i32 to ISelTom Stellard2012-05-174-17/+16
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* radeon/llvm: Remove sub patterns from AMDILInstrPatterns.tdTom Stellard2012-05-172-21/+1
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* radeon/llvm: Add custom SDNodes for MAXTom Stellard2012-05-1710-10/+108
| | | | | We now lower the various intrinsics for max to SDNodes and then use tablegen patterns to lower the SDNodes to instructions.
* radeon/llvm: add support for texture offsets, fix TEX_LDVadim Girlin2012-05-154-10/+51
| | | | | Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: add SET_GRADIENTS*, fix SAMPLE_GVadim Girlin2012-05-155-4/+96
| | | | | Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: increase const regs countVadim Girlin2012-05-151-1/+1
| | | | | Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: use IntrNoMem property for intrinsics where possibleVadim Girlin2012-05-156-95/+158
| | | | | Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: use correct intrinsic for CEILVadim Girlin2012-05-152-3/+3
| | | | | | | Should be round_posinf instead of round_neginf. Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: improve ABS_i32 loweringVadim Girlin2012-05-151-13/+5
| | | | | | | | | We can save one instruction by lowering it to: SUB_INT tmp, 0, src MAX_INT dst, src, tmp Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: fix BUILD_VECTOR lowering for replicated valueVadim Girlin2012-05-151-0/+2
| | | | | | | We expect that all elements will be assigned even if they are equal Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: add names for AMDGPU* passesVadim Girlin2012-05-152-0/+5
| | | | | Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: add generated files to .gitignoreVadim Girlin2012-05-151-0/+18
| | | | | Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeonsi: Flesh out shader interpolation related code.Michel Dänzer2012-05-142-0/+21
| | | | Handle perspective interpolation and ceontroid vs. center.
* radeon/llvm: Coding style fixes for R600CodeEmitter.cppTom Stellard2012-05-141-148/+90
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* radeon/llvm: Lower bitcast instructions to copiesTom Stellard2012-05-141-0/+10
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* radeon/llvm: More comments and cleanupsTom Stellard2012-05-1122-163/+190
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* radeon/llvm: Fix Evergreen/Cayman tablegen predicatesTom Stellard2012-05-111-1/+3
| | | | Some Evergreen/Cayman instructions were being enabled for SI.
* radeon/llvm: Remove AMDILMCCodeEmitter.cppTom Stellard2012-05-102-158/+0
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* radeon/llvm: Remove SILowerShaderInstructions.cppTom Stellard2012-05-104-81/+0
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* radeonsi/llvm: Move lowering of RETURN to ConvertToISA passTom Stellard2012-05-102-11/+2
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* radeon/llvm: Add some commentsTom Stellard2012-05-1064-422/+393
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* radeon/llvm: Move util functions into AMDGPU namespaceTom Stellard2012-05-103-39/+37
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* radeon/llvm: Auto-encode RAT_WRITE_CACHELESS_egTom Stellard2012-05-102-17/+0
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* radeon/llvm: Delete all instructions that have been custom loweredTom Stellard2012-05-101-4/+1
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* radeon/llvm: Remove AMDGPUConstants.pmTom Stellard2012-05-092-45/+23
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* radeon/llvm: Don't rely on tablegen for lowering int_AMDGPU_load_constTom Stellard2012-05-095-38/+20
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* radeon/llvm: Make sure the LOAD_CONST def uses the isSI predicateTom Stellard2012-05-092-7/+7
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* radeon/llvm: Remove AMDILUtilityFunctions.cppTom Stellard2012-05-0813-1041/+399
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* radeon/llvm: Remove some unused functions from AMDILInstrInfoTom Stellard2012-05-082-164/+0
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* radeon/llvm: Add some comments and fix coding styleTom Stellard2012-05-088-42/+41
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* radeon/llvm: Remove the EXPORT_REG instructionTom Stellard2012-05-089-109/+6
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