| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | radeon/llvm: Use a custom inserter to lower RESERVE_REG | Tom Stellard | 2012-05-08 | 9 | -21/+81 | |
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| * | radeon/llvm: Use a custom inserter to lower STORE_OUTPUT | Tom Stellard | 2012-05-08 | 4 | -34/+23 | |
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| * | radeon/llvm: Remove AMDGPULowerShaderInstructions class | Tom Stellard | 2012-05-08 | 6 | -86/+4 | |
| | | | | | It is no longer used. | |||||
| * | radeon/llvm: Use a custom inserter to lower LOAD_INPUT | Tom Stellard | 2012-05-08 | 4 | -39/+15 | |
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| * | radeon/llvm: Remove the ReorderPreloadInstructions pass | Tom Stellard | 2012-05-08 | 9 | -100/+4 | |
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| * | radeon/llvm: Remove old comment from AMDIL.h | Tom Stellard | 2012-05-08 | 1 | -5/+0 | |
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| * | radeon/llvm: add suport for cube textures | Vadim Girlin | 2012-05-08 | 1 | -1/+91 | |
| | | | | | Signed-off-by: Vadim Girlin <[email protected]> | |||||
| * | radeon/llvm: add support for CUBE ALU instruction | Vadim Girlin | 2012-05-08 | 5 | -21/+63 | |
| | | | | | Signed-off-by: Vadim Girlin <[email protected]> | |||||
| * | radeon/llvm: add support for some ALU instructions | Vadim Girlin | 2012-05-08 | 4 | -13/+293 | |
| | | | | | | | | | Add support for IABS, NOT, AND, XOR, OR, UADD, UDIV, IDIV, MOD, UMOD, INEG, I2F, U2F, F2U, F2I, USEQ, USGE, USLT, USNE, ISGE, ISLT, ROUND, MIN, MAX, IMIN, IMAX, UMIN, UMAX Signed-off-by: Vadim Girlin <[email protected]> | |||||
| * | radeon/llvm: add missing cases for BREAK/CONTINUE | Vadim Girlin | 2012-05-08 | 2 | -0/+3 | |
| | | | | | Signed-off-by: Vadim Girlin <[email protected]> | |||||
| * | radeon/llvm: add support for AHSR/LSHR/LSHL instructions | Vadim Girlin | 2012-05-08 | 4 | -0/+53 | |
| | | | | | Signed-off-by: Vadim Girlin <[email protected]> | |||||
| * | radeon/llvm: add support for TXQ/TXF/DDX/DDY instructions | Vadim Girlin | 2012-05-08 | 4 | -4/+39 | |
| | | | | | Signed-off-by: Vadim Girlin <[email protected]> | |||||
| * | radeon/llvm: add support for VertexID, InstanceID | Vadim Girlin | 2012-05-08 | 2 | -0/+16 | |
| | | | | | Signed-off-by: Vadim Girlin <[email protected]> | |||||
| * | radeon/llvm: fix live-in handling for inputs | Vadim Girlin | 2012-05-08 | 2 | -2/+3 | |
| | | | | | | | Set the input registers as live-in for entry basic block. Signed-off-by: Vadim Girlin <[email protected]> | |||||
| * | radeon/llvm: add support for v4i32 | Vadim Girlin | 2012-05-08 | 4 | -5/+20 | |
| | | | | | Signed-off-by: Vadim Girlin <[email protected]> | |||||
| * | radeon/llvm: fix ABS_i32 instruction lowering | Vadim Girlin | 2012-05-08 | 1 | -2/+2 | |
| | | | | | | | Swap source operands. Signed-off-by: Vadim Girlin <[email protected]> | |||||
| * | radeon/llvm: use integer comparison for IF | Vadim Girlin | 2012-05-08 | 1 | -2/+4 | |
| | | | | | | | | Replacing "float equal to 1.0f" with "int not equal to 0". This should help for further optimization of boolean computations. Signed-off-by: Vadim Girlin <[email protected]> | |||||
| * | radeon/llvm: use bitcasts for integers | Vadim Girlin | 2012-05-08 | 2 | -4/+70 | |
| | | | | | | | | | | We're using float as default type, so basically for every instruction that wants other types for dst/src operands we need to perform the bitcast to/from default float. Currently bitcast produces no-op MOV instruction, will be eliminated later. Signed-off-by: Vadim Girlin <[email protected]> | |||||
| * | radeon/llvm: Remove references to DebugFlag and isCurrentDebugType() | Tom Stellard | 2012-05-07 | 4 | -22/+3 | |
| | | | | | | | | These weren't being used at all and they were causing build failures when LLVM was built with NDEBUG defined and mesa was not. https://bugs.freedesktop.org/show_bug.cgi?id=49110 | |||||
| * | r600g/llvm: Lower ULT A, B, C to SETGT_UINT A, C, B | Tom Stellard | 2012-05-03 | 1 | -0/+7 | |
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| * | r600g/llvm: Don't duplicate R600 intrinsics installed by LLVM | Tom Stellard | 2012-05-03 | 4 | -0/+26 | |
| | | | | | | | | At this point, in order for OpenCL to work correctly with r600g, OpenCL specific intrinsics need to be defined in the LLVM tree. So, we need to check for these intrinsics in the LLVM include directory to make sure not to re-define them. | |||||
| * | radeon/llvm: Fix MachineInstr dump | Tom Stellard | 2012-05-02 | 2 | -8/+9 | |
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| * | radeon/llvm: Fix build for updated LLVM 3.1 release branch | Tom Stellard | 2012-05-01 | 2 | -18/+18 | |
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| * | radeon/llvm: Add subtarget feature: DumpCode | Tom Stellard | 2012-05-01 | 5 | -6/+9 | |
| | | | | | | | With this feature enabled, the LLVM backend will dump the MachineIntrs prior to emitting code. The mesa env variable R600_DUMP_SHADERS will enable this feature in the backend. | |||||
| * | r600g/llvm: Remove unnecessary dynamic casts | Dragomir Ivanov | 2012-04-30 | 1 | -5/+5 | |
| | | | | | | | | When the result of dynamic_cast is not checked, it can be replaced with static_cast Signed-off-by: Tom Stellard <[email protected]> | |||||
| * | r600g/llvm: Add pattern for llvm.AMDGPU.kill v2 | Dragomir Ivanov | 2012-04-30 | 2 | -1/+6 | |
| | | | | | Signed-off-by: Tom Stellard <[email protected]> | |||||
| * | r600g/llvm: Fix handling of MASK_WRITE instructions | Tom Stellard | 2012-04-30 | 2 | -1/+3 | |
| | | | | | | | We can't delete MASK_WRITE instructions from the program, because this will cause instructions being masked by MASK_WRITE to be marked dead and then deleted in the dce pass. | |||||
| * | radeon/llvm: Use a custom emit function for TGSI_OPCODE_KIL | Tom Stellard | 2012-04-30 | 1 | -1/+16 | |
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| * | radeonsi/llvm: Silence a warning | Tom Stellard | 2012-04-25 | 1 | -0/+1 | |
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| * | radeon/llvm: Remove unused header files | Tom Stellard | 2012-04-25 | 2 | -115/+0 | |
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| * | radeon/llvm: Remove AMDILMachineFunctionInfo.cpp | Tom Stellard | 2012-04-25 | 14 | -1176/+6 | |
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| * | radeon/llvm: Remove AMDILModuleInfo.cpp | Tom Stellard | 2012-04-25 | 4 | -1432/+0 | |
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| * | radeon/llvm: Remove AMDILELFWriterInfo.cpp | Tom Stellard | 2012-04-25 | 5 | -137/+1 | |
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| * | radeon/llvm: Remove AMDILLiteralManager.cpp | Tom Stellard | 2012-04-25 | 4 | -129/+0 | |
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| * | radeon/llvm: Remove AMDILInliner.cpp | Tom Stellard | 2012-04-25 | 5 | -276/+0 | |
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| * | radeon/llvm: Remove AMDILBarrierDetect.cpp | Tom Stellard | 2012-04-25 | 5 | -259/+0 | |
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| * | radeon/llvm: Remove AMDILPrintfConvert.cpp | Tom Stellard | 2012-04-25 | 5 | -295/+0 | |
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| * | radeon/llvm: Remove GlobalManager and KernelManager | Tom Stellard | 2012-04-25 | 11 | -3275/+23 | |
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| * | radeon/llvm: Remove AsmPrinter files | Tom Stellard | 2012-04-25 | 5 | -443/+0 | |
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| * | radeon/llvm: Remove IOExpansion files | Tom Stellard | 2012-04-25 | 15 | -4048/+0 | |
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| * | radeon/llvm: Remove AMDILPointerManager.cpp | Tom Stellard | 2012-04-25 | 10 | -2789/+0 | |
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| * | radeonsi/llvm: Fix initialization of SIMachineFunctionInfo | Tom Stellard | 2012-04-25 | 1 | -4/+4 | |
| | | | | | | SIMachineFunctionInfo needs to be initialized before any of the AMDIL passes. | |||||
| * | radeon/llvm: Don't print an error message when there is no error | Tom Stellard | 2012-04-23 | 1 | -2/+1 | |
| | | | | | | A blank line with an empty error message was being printed even when the target lookup succeeded. | |||||
| * | radeon/llvm: Lower VCREATE_v4f32 for R600 and SI | Tom Stellard | 2012-04-23 | 5 | -33/+22 | |
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| * | r600g/llvm: Let ISel handle lowering to {INSERT,EXTRACT}_SUBREG | Tom Stellard | 2012-04-23 | 6 | -88/+37 | |
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| * | r600g/llvm: Only emit an instruction's explicit operands | Tom Stellard | 2012-04-23 | 1 | -2/+2 | |
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| * | r600g/llvm: Handle copies between vector registers | Tom Stellard | 2012-04-23 | 2 | -2/+21 | |
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| * | r600g/llvm: Remove debugging hack from R600InstrInfo::copyPhysReg() | Tom Stellard | 2012-04-23 | 1 | -4/+0 | |
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| * | r600g/llvm: Tell the code emitter to ignore KILL and BUNDLE | Tom Stellard | 2012-04-23 | 1 | -1/+3 | |
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| * | r600/llvm: Add LOAD_VTX instruction | Tom Stellard | 2012-04-23 | 1 | -0/+13 | |
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