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* r600g,radeonsi: Only set use_staging_texture = TRUE onceMichel Dänzer2014-10-151-8/+5
| | | | | | No need to check for setting the flag after we set it already. Reviewed-by: Marek Olšák <[email protected]>
* r600g,radeonsi: Use staging texture for transfers if any miplevel is tiledMichel Dänzer2014-10-151-1/+1
| | | | | | | We set the NO_CPU_ACCESS flag for BO allocation in that case, so direct CPU access may not work. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: remove shader->input[] and output[] arrays and dependenciesMarek Olšák2014-10-121-1/+2
| | | | | | | | | They were reinventing tgsi_shader_info. They are unused now. radeon_llvm_context::load_input can be NULL if input fetching is implemented in some other way. Reviewed-by: Michel Dänzer <[email protected]>
* r600g,radeonsi: Always use GTT again for PIPE_USAGE_STREAM buffersMichel Dänzer2014-10-091-1/+3
| | | | | | | | | Putting those in VRAM can cause long pauses due to buffers being moved into / out of VRAM. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84662 Cc: [email protected] Reviewed-by: Alex Deucher <[email protected]>
* radeonsi/compute: do CS partial flush with si_emit_cache_flushMarek Olšák2014-09-241-0/+1
| | | | | Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeonsi/compute: flush caches with si_emit_cache_flushMarek Olšák2014-09-241-0/+3
| | | | | Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* r600g,radeonsi: add debug option which forces DMA for copy_region and blitMarek Olšák2014-09-122-1/+3
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* radeon/uvd: use PIPE_USAGE_STAGING for msg&fb buffersChristian König2014-09-111-1/+1
| | | | | | | | That better matches the actual userspace use case, the kernel will force it to VRAM if the hardware requires it. Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeon/video: use the hw to initial clear the buffersChristian König2014-09-113-10/+8
| | | | | | | Less CPU overhead and avoids contention over CPU accessible memory on startup. Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeon/video: use more of the common buffer code v2Christian König2014-09-116-67/+62
| | | | | | | | | In preparation to using buffers clears with the hw engine(s). v2: split out flipping to using hw buffer clears. Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* r600g,radeonsi: Set RADEON_GEM_NO_CPU_ACCESS flag for tiled BOsMichel Dänzer2014-09-101-0/+1
| | | | | | | This lets the kernel know that such BOs can be pinned outside of the CPU accessible part of VRAM. Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: ship all files in the tarballEmil Velikov2014-09-052-7/+20
| | | | | | | | | - include all headers in Makefile.sources - sort the list(s) - bundle the android buildscript & LLVM note Signed-off-by: Emil Velikov <[email protected]> Acked-by: Matt Turner <[email protected]>
* r600g,radeonsi: make sure there's enough CS space before resuming queriesMarek Olšák2014-09-041-0/+28
| | | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83432 Cc: "10.2 10.3" <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* Revert "r600g,radeonsi: initialize HTILE to fully-expanded state"Marek Olšák2014-09-041-3/+1
| | | | | | | | This reverts commit f05fe294e7e8dfb08be172f426252192c0ba17ab. Apparently the hw doesn't like this. Revert to the "cleared" state. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83418
* r600g,radeonsi: Preserve existing buffer flagsMichel Dänzer2014-09-031-3/+3
| | | | | | | | The default case was accidentally clearing RADEON_FLAG_CPU_ACCESS from the previous fall-through cases. Reported-by: Mathias Fröhlich <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* r600g,radeonsi: Inform the kernel if a BO will likely be accessed by the CPUMichel Dänzer2014-09-021-9/+14
| | | | | | | This allows the kernel to prevent such BOs from ever being stored in the CPU inaccessible part of VRAM. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: implement EXPCLEAR optimization for depthMarek Olšák2014-09-011-0/+1
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* r600g,radeonsi: initialize HTILE to fully-expanded stateMarek Olšák2014-09-011-1/+3
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* r600g: use HTILE allocator from SIMarek Olšák2014-09-011-41/+19
| | | | | | | | | | | | It's almost the same. This enables tiling for HTILE. It also enables Hyper-Z for other texture targets (1D, 1D_ARRAY, 2D_ARRAY, CUBE, CUBE_ARRAY, 3D, RECT). 2D array depth textures are tested by Unigine Sanctuary and my new piglit test. Acked-by: Michel Dänzer <[email protected]>
* gallium/radeon: cleanup header inclusionEmil Velikov2014-08-287-7/+7
| | | | | | | | | | | | | | - Add top_srcdir/src/gallium/winsys to GALLIUM_DRIVER_C{XXFLAGS}. - Remove top_srcdir/src/gallium/drivers/radeon from the includes. As a result: - Common radeon headers are prefixed with 'radeon/' - Winsys header inclusion is prefixed 'radeon/drm' Cc: Marek Olšák <[email protected]> Cc: Michel Dänzer <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeon/uvd: remove comment about RV770Alex Deucher2014-08-271-1/+0
| | | | | | | It doesn't seem to support field based decode after testing. Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/uvd: fix field handling on R6XX style UVDChristian König2014-08-261-2/+5
| | | | | | The first UVD generation can only do frame based output. Signed-off-by: Christian König <[email protected]>
* radeon: Add work-around for missing Hainan support in clang < 3.6 v2Tom Stellard2014-08-211-1/+14
| | | | | | | | | v2: - Add missing break. https://bugs.freedesktop.org/show_bug.cgi?id=82709 CC: "10.2" <[email protected]>
* gallium/radeon: Do not use u_upload_mgr for buffer downloadsNiels Ole Salscheider2014-08-191-12/+8
| | | | | | | | | | | | | | Instead create a staging texture with pipe_buffer_create and PIPE_USAGE_STAGING. u_upload_mgr sets the usage of its staging buffer to PIPE_USAGE_STREAM. But since 150ac07b855b5c5f879bf6ce9ca421ccd1a6c938 CPU -> GPU streaming buffers are created in VRAM. Therefore the staging texture (in VRAM) does not offer any performance improvements for buffer downloads. Signed-off-by: Niels Ole Salscheider <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeonsi: use r600_draw_rectangle from r600gMarek Olšák2014-08-192-0/+72
| | | | | | Rectangles are easier than triangles for the rasterizer. Reviewed-by: Michel Dänzer <[email protected]>
* r600g: implement invalidation of texture buffer objectsMarek Olšák2014-08-142-0/+7
| | | | | | This fixes piglit spec/ARB_texture_buffer_object/data-sync. Reviewed-by: Alex Deucher <[email protected]>
* radeon/compute: Fix reported values for MAX_GLOBAL_SIZE and MAX_MEM_ALLOC_SIZETom Stellard2014-08-131-13/+19
| | | | | | | | There is a hard limit in older kernels of 256 MB for buffer allocations, so report this value as MAX_MEM_ALLOC_SIZE and adjust MAX_GLOBAL_SIZE to statisfy requirements of OpenCL. CC: "10.2" <[email protected]>
* android: gallium/radeon: attempt to fix the android buildPaulo Sergio Travaglia2014-08-131-0/+38
| | | | | | | | | | | - include the correct folders - add a new buildscript for the common radeon folder v2: Use the installed libdrm headers over the DRM_TOP ones. Cc: "10.1 10.2" <[email protected]> [Emil Velikov] Split up and add commit message. Signed-off-by: Emil Velikov <[email protected]>
* gallium/radeon: Set gpu_address to 0 if r600_virtual_address is falseNiels Ole Salscheider2014-08-101-0/+2
| | | | | | | | | | | Without this patch I get the following during DMA transfers: [drm:radeon_cs_ib_chunk] *ERROR* Invalid command stream ! radeon 0000:01:00.0: CP DMA dst buffer too small (21475829792 4096) This is a fixup for e878e154cdfd4dbb5474f776e0a6d86fcb983098. Signed-off-by: Niels Ole Salscheider <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeonsi: fix CMASK and HTILE allocation on TahitiMarek Olšák2014-08-091-2/+2
| | | | | | | | | | | | | | | | Tahiti has 12 tile pipes, but P8 pipe config. It looks like there is no way to get the pipe config except for reading GB_TILE_MODE. The TILING_CONFIG ioctl doesn't return more than 8 pipes, so we can't use that for Hawaii. This fixes a regression caused by 9b046474c95f15338d4c748df9b62871bba6f36f on Tahiti. v2: add an assertion and print an error on failure Cc: [email protected] Reviewed-by: Michel Dänzer <[email protected]>
* gallium/radeon: remove r600_resource_vaMarek Olšák2014-08-091-9/+0
| | | | | Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* gallium/radeon: use gpu_address from r600_resourceMarek Olšák2014-08-093-21/+14
| | | | | Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* gallium/radeon: store VM address in r600_resourceMarek Olšák2014-08-093-2/+7
| | | | | | | This will help to get rid of the buffer_get_virtual_address calls. Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: always prefer SWITCH_ON_EOP(0) on CIKMarek Olšák2014-08-092-1/+2
| | | | | | | | | | | | | | The code is rewritten to take known constraints into account, while always using 0 by default. This should improve performance for multi-SE parts in theory. A debug option is also added for easier debugging. (If there are hangs, use the option. If the hangs go away, you have found the problem.) Reviewed-by: Alex Deucher <[email protected]> v2: fix a typo, set max_se for evergreen GPUs according to the kernel driver
* r600g/radeonsi: Prefer VRAM for CPU -> GPU streaming buffersMichel Dänzer2014-08-011-4/+11
| | | | Reviewed-by: Marek Olšák <[email protected]>
* r600g/radeonsi: Reduce or even drop special treatment of persistent mappingsMichel Dänzer2014-08-011-4/+8
| | | | Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: Add some Emacs .dir-locals.el filesMichel Dänzer2014-07-291-0/+11
| | | | | | Based on the toplevel one but adapted to the driver/winsys coding styles. Reviewed-by: Marek Olšák <[email protected]>
* r600g,radeonsi: switch all occurences of array_size to util_max_layerMarek Olšák2014-07-281-3/+6
| | | | | | | | | | | | | | | | | | This fixes 3D texture support in all these cases, because array_size is 1 with 3D textures and depth0 actually contains the "array size". util_max_layer is universal and returns the last layer index for any texture target. A lot of the cases below can't actually be hit with 3D textures, but let's be consistent. This fixes a failure in: piglit layered-rendering/clear-color-all-types 3d single_level for r600g and radeonsi, which was caused by an incorrect CMASK size calculation. Cc: [email protected] Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: fix occlusion queries on HawaiiMarek Olšák2014-07-281-1/+7
| | | | | | | This was just a guess - and it worked! Cc: [email protected] Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: fix a hang with streamout on HawaiiMarek Olšák2014-07-281-0/+1
| | | | | | | | | | | I actually couldn't reproduce this one, but internal docs recommend this workaround. Better safe than sorry. Also, the number of dwords for the sync packets is increased by 4 instead of 2, because it wasn't bumped last time when a new packet was added there. Cc: [email protected] Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: fix CMASK and HTILE calculations for HawaiiMarek Olšák2014-07-281-2/+2
| | | | | | | | | | This fixes the checkerboard pattern in glxgears and anything that triggers fast color clear. num_channels is always <= 8, but Hawaii has 16 pipes. Cc: [email protected] Reviewed-by: Alex Deucher <[email protected]>
* r600g,radeonsi: add debug flags which disable tilingMarek Olšák2014-07-283-13/+24
| | | | Reviewed-by: Alex Deucher <[email protected]>
* gallium: Add PIPE_CAP_COMPUTE_IMAGES_SUPPORTEDTom Stellard2014-07-251-0/+7
| | | | | Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* radeon/llvm: fix formattingGrigori Goronzy2014-07-231-10/+14
| | | | | | | Use K&R and same indent as most other code. No functional change intended. Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: enable unsafe math for graphics shadersGrigori Goronzy2014-07-231-0/+5
| | | | | | | | | | | Accuracy of some operations was recently improved in the R600 backend, at the cost of slower code. This is required for compute shaders, but not for graphics shaders. Add unsafe-fp-math hint to make LLVM generate faster but possibly less accurate code. Piglit didn't indicate any regressions. Reviewed-by: Tom Stellard <[email protected]>
* r600g/radeonsi: Use write-combined CPU mappings of some BOs in GTTMichel Dänzer2014-07-236-14/+28
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/compute: Share COMPUTE_DBG macro with r600gTom Stellard2014-07-211-0/+5
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Read rodata from ELF and append it to the end of shadersTom Stellard2014-07-212-0/+10
| | | | | | | The is used for programs that have arrays of constants that are accessed using dynamic indices. The shader will compute the base address of the constants and then access them using SMRD instructions.
* radeonsi: assume LLVM 3.4.2 is always presentMarek Olšák2014-07-181-7/+0
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeon/llvm: Fix LLVM diagnostic error reportingTom Stellard2014-07-151-7/+4
| | | | | | | We were trying to print the error message after disposing the message object. Tested-by and Reviewed-by: Aaron Watry <[email protected]>
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