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* radeon/llvm: Add instruction defs for branches on SITom Stellard2012-07-273-17/+126
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* radeon/llvm: Fix VOPC and V_CNDMASK encodingTom Stellard2012-07-274-10/+13
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* radeon/llvm: Assert if we try to copy SCC regTom Stellard2012-07-271-0/+6
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* radeon/llvm: Add SI DAG optimizations for setcc, select_ccTom Stellard2012-07-272-0/+54
| | | | | These are needed for correctly lowering branch instructions in some cases.
* radeon/llvm: Add support for encoding SI branch instructionsTom Stellard2012-07-271-15/+35
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* radeon/llvm: Add special nodes for SALU operations on VCCTom Stellard2012-07-276-1/+89
| | | | | | | The VCC register is tricky because the SALU views it as 64-bit, but the VALU views it as 1-bit. In order to deal with this we've added some special bitcast and binary operations to help convert from the 64-bit SALU view to the 1-bit VALU view and vice versa.
* radeon/llvm: Add i1 registers for SI.Tom Stellard2012-07-271-0/+2
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* radeon/llvm: Fix CCReg definitions on SITom Stellard2012-07-272-3/+10
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* radeon/llvm: Add bitconvert patterns for SITom Stellard2012-07-271-0/+6
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* radeon/llvm: Add custom lowering for SELECT_CC nodes on SITom Stellard2012-07-272-0/+20
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* radeon/llvm: Move conditional pattern leafs to common tablegen fileTom Stellard2012-07-272-41/+41
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* radeon/llvm: Implement getSetCCResultType for SITom Stellard2012-07-272-0/+6
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* radeon/llvm: Custom lower BR_CC for SITom Stellard2012-07-272-0/+41
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* radeon/llvm: Move lowering of BR_CC node to R600ISelLoweringTom Stellard2012-07-274-31/+31
| | | | | SI will handle BR_CC different from R600, so we need to move it out of the shared instruction selector.
* radeon/llvm: Move lowering of SETCC node to R600ISelLoweringTom Stellard2012-07-274-38/+29
| | | | | SI will handle SETCC different from R600, so we need to move it out of the shared instruction selector.
* radeon/llvm: Use correct node type when lowering SETCCTom Stellard2012-07-271-0/+1
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* radeon/llvm: Move LowerSELECT_CC into R600ISelLoweringTom Stellard2012-07-274-111/+112
| | | | | SI will handle SELECT_CC different from R600, so we need to move it out of the shared instruction selector.
* radeon/llvm: Fix a bug with IF LOGICALNZ with int operandVincent Lejeune2012-07-232-3/+5
| | | | Signed-off-by: Tom Stellard <[email protected]>
* radeon/llvm: Fix CR/LF in AMDILSIDevice.hAndreas Boll2012-07-131-1/+1
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* radeon/llvm: Clean up AMDILIntrinsicInfo.cppTom Stellard2012-07-132-84/+5
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* radeon/llvm: Coding style fixesTom Stellard2012-07-132-409/+325
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* radeon/llvm: Don't use lp_build_swizzle_aos() for swizzlesTom Stellard2012-07-121-8/+13
| | | | | | | This function assumes that lp_build_context::type is a vector type, which is not true for r600 or radeonsi. This fixes an assertion failure using glamor 2D accel.
* radeon/llvm: Use multiclasses for floating point loadsTom Stellard2012-07-117-50/+46
| | | | | | | The original strategy for handling floating point loads, which was to lower (f32 load) to (f32 bitcast (i32 load)) wasn't really working. The main problem was that the DAG legalizer couldn't handle replacing a node with two results (load) with a node with only one result (bitcast).
* radeon/llvm: Don't set the IMM bit in SMRD instruction definitions.Tom Stellard2012-07-111-7/+2
| | | | The IMM bit is already being set in SICodeEmitter.
* radeon/llvm: Rename namespace from AMDIL to AMDGPUTom Stellard2012-07-0925-360/+361
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* radeon/llvm: Enable vec4 loads on R600Tom Stellard2012-06-293-0/+20
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* radeon/llvm: Enable floating point stores on R600Tom Stellard2012-06-291-0/+6
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* radeon/llvm: Handle floating point loads on R600Tom Stellard2012-06-292-0/+31
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* radeon/llvm: Expand UDIV and UREM nodesTom Stellard2012-06-291-4/+3
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* radeon/llvm: Emit raw ISA for vertex fetch instructionsTom Stellard2012-06-292-61/+99
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* radeon/llvm: Turn on the BitExtract peephole optimizationTom Stellard2012-06-212-5/+32
| | | | | Thie BitExtract optimization folds a mask and shift operation together into a single instruction (BFE_UINT).
* radeon/llvm: Lower ROTL to BIT_ALIGNTom Stellard2012-06-216-1/+54
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* radeon/llvm: Use the VLIW Scheduler for R600->NITom Stellard2012-06-2112-8/+75
| | | | | | | | | | | | | | | | | | | It's not optimal, but it's better than the register pressure scheduler that was previously being used. The VLIW scheduler currently ignores all the complicated instruction groups restrictions and just tries to fill the instruction groups with as many instructions as possible. Though, it does know enough not to put two trans only instructions in the same group. We are able to ignore the instruction group restrictions in the LLVM backend, because the finalizer in r600_asm.c will fix any illegal instruction groups the backend generates. Enabling the VLIW scheduler improved the run time for a sha1 compute shader by about 50%. I'm not sure what the impact will be for graphics shaders. I tested Lightsmark with the VLIW scheduler enabled and the framerate was about the same, but it might help apps that use really big shaders.
* radeon/llvm: Fix CR/LF in Processors.tdTörök Edwin2012-06-191-17/+17
| | | | Signed-off-by: Tom Stellard <[email protected]>
* radeon/llvm: Fix sin/cos codegen on R700Török Edwin2012-06-191-19/+24
| | | | | | | | | | Based on https://bugs.freedesktop.org/show_bug.cgi?id=50317#c4 Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=50316 https://bugs.freedesktop.org/show_bug.cgi?id=50317 Signed-off-by: Tom Stellard <[email protected]>
* radeon/llvm: Update comment in AMDGPU.tdTom Stellard2012-06-181-2/+3
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* radeon/llvm: Remove unused AMDIL TableGen definitonsTom Stellard2012-06-1818-6140/+26
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* radeon/llvm: Eliminate getRegClassFromType() functionTom Stellard2012-06-181-42/+1
| | | | We can use TargetLowering::getRegClassFor() instead.
* radeon/llvm: Remove deadcode from AMDILISelLowering.cppTom Stellard2012-06-184-1687/+0
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* radeonsi: Handle SUB_f32.Thomas Stellard2012-06-122-2/+3
| | | | | Signed-off-by: Thomas Stellard <[email protected]> Signed-off-by: Michel Dänzer <[email protected]>
* radeonsi: Only dump shaders with environment variable RADEON_DUMP_SHADERS=1.Michel Dänzer2012-06-121-1/+5
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* automake: Globally add stub automake targets to the old Makefiles.Eric Anholt2012-06-111-3/+0
| | | | | | | | | I tried to update all the old Makefiles that included the default config to be sure they had a default target if they didn't previously have one, since this new all target will always point at it. Almost everything had one. Reviewed-by: Kenneth Graunke <[email protected]>
* radeon/llvm: Emulate RECIP_UINT instruction on CaymanTom Stellard2012-06-062-4/+13
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* radeon/llvm: Remove some duplicate code in the R600 CodeEmitterTom Stellard2012-06-061-9/+3
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* radeon/llvm: Fix MULLO* instructions on CaymanTom Stellard2012-06-064-14/+53
| | | | | On Cayman, the MULLO* instructions must fill all slots in an instruction group.
* r600g: Compute support for CaymanTom Stellard2012-06-061-48/+44
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* radeon/llvm: Remove obselete hooks for the ConvertToISA passTom Stellard2012-06-066-87/+1
| | | | | | We can't remove this pass yet, because we need it to convert AMDIL registers in BRANCH* instructions, but we don't need it for instruction conversion any more.
* radeon/llvm: Remove AMDIL MOVE* instructionsTom Stellard2012-06-065-20/+2
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* radeon/llvm: Add isMov() to AMDILInstrInfoTom Stellard2012-06-066-11/+34
| | | | | This enables the CFGStructurizer to work without the AMDIL::MOV* instructions.
* radeon/llvm: Remove deadcode from the AMDILISelLowering classTom Stellard2012-06-062-203/+0
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