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* radeon/llvm: Add DAG nodes for MIN instructionsTom Stellard2012-05-176-14/+38
| | | | Also, remove the AMDIL MIN* instruction defs.
* radeon/llvm: Lower lrp intrinsic during ISelTom Stellard2012-05-173-7/+19
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* radeon/llvm: Remove AMDIL MAD instruction defsTom Stellard2012-05-176-7/+14
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* radeon/llvm: Remove AMDIL MUL_IEEE* instructionsTom Stellard2012-05-173-7/+3
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* radeon/llvm: Expand fsub during ISelTom Stellard2012-05-172-11/+2
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* radeon/llvm: Remove AMDIL floating-point ADD instruction defsTom Stellard2012-05-175-8/+9
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* radeon/llvm: Remove AMDIL CMOVLOG* instruction defsTom Stellard2012-05-174-26/+6
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* radeon/llvm: Move lowering of ABS_i32 to ISelTom Stellard2012-05-174-17/+16
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* radeon/llvm: Remove sub patterns from AMDILInstrPatterns.tdTom Stellard2012-05-172-21/+1
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* radeon/llvm: Add custom SDNodes for MAXTom Stellard2012-05-1710-10/+108
| | | | | We now lower the various intrinsics for max to SDNodes and then use tablegen patterns to lower the SDNodes to instructions.
* radeon/llvm: add support for texture offsets, fix TEX_LDVadim Girlin2012-05-154-10/+51
| | | | | Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: add SET_GRADIENTS*, fix SAMPLE_GVadim Girlin2012-05-155-4/+96
| | | | | Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: increase const regs countVadim Girlin2012-05-151-1/+1
| | | | | Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: use IntrNoMem property for intrinsics where possibleVadim Girlin2012-05-156-95/+158
| | | | | Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: use correct intrinsic for CEILVadim Girlin2012-05-152-3/+3
| | | | | | | Should be round_posinf instead of round_neginf. Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: improve ABS_i32 loweringVadim Girlin2012-05-151-13/+5
| | | | | | | | | We can save one instruction by lowering it to: SUB_INT tmp, 0, src MAX_INT dst, src, tmp Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: fix BUILD_VECTOR lowering for replicated valueVadim Girlin2012-05-151-0/+2
| | | | | | | We expect that all elements will be assigned even if they are equal Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: add names for AMDGPU* passesVadim Girlin2012-05-152-0/+5
| | | | | Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: add generated files to .gitignoreVadim Girlin2012-05-151-0/+18
| | | | | Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeonsi: Flesh out shader interpolation related code.Michel Dänzer2012-05-142-0/+21
| | | | Handle perspective interpolation and ceontroid vs. center.
* radeon/llvm: Coding style fixes for R600CodeEmitter.cppTom Stellard2012-05-141-148/+90
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* radeon/llvm: Lower bitcast instructions to copiesTom Stellard2012-05-141-0/+10
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* radeon/llvm: More comments and cleanupsTom Stellard2012-05-1122-163/+190
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* radeon/llvm: Fix Evergreen/Cayman tablegen predicatesTom Stellard2012-05-111-1/+3
| | | | Some Evergreen/Cayman instructions were being enabled for SI.
* radeon/llvm: Remove AMDILMCCodeEmitter.cppTom Stellard2012-05-102-158/+0
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* radeon/llvm: Remove SILowerShaderInstructions.cppTom Stellard2012-05-104-81/+0
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* radeonsi/llvm: Move lowering of RETURN to ConvertToISA passTom Stellard2012-05-102-11/+2
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* radeon/llvm: Add some commentsTom Stellard2012-05-1064-422/+393
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* radeon/llvm: Move util functions into AMDGPU namespaceTom Stellard2012-05-103-39/+37
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* radeon/llvm: Auto-encode RAT_WRITE_CACHELESS_egTom Stellard2012-05-102-17/+0
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* radeon/llvm: Delete all instructions that have been custom loweredTom Stellard2012-05-101-4/+1
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* radeon/llvm: Remove AMDGPUConstants.pmTom Stellard2012-05-092-45/+23
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* radeon/llvm: Don't rely on tablegen for lowering int_AMDGPU_load_constTom Stellard2012-05-095-38/+20
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* radeon/llvm: Make sure the LOAD_CONST def uses the isSI predicateTom Stellard2012-05-092-7/+7
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* radeon/llvm: Remove AMDILUtilityFunctions.cppTom Stellard2012-05-0813-1041/+399
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* radeon/llvm: Remove some unused functions from AMDILInstrInfoTom Stellard2012-05-082-164/+0
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* radeon/llvm: Add some comments and fix coding styleTom Stellard2012-05-088-42/+41
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* radeon/llvm: Remove the EXPORT_REG instructionTom Stellard2012-05-089-109/+6
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* radeon/llvm: Use a custom inserter to lower RESERVE_REGTom Stellard2012-05-089-21/+81
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* radeon/llvm: Use a custom inserter to lower STORE_OUTPUTTom Stellard2012-05-084-34/+23
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* radeon/llvm: Remove AMDGPULowerShaderInstructions classTom Stellard2012-05-086-86/+4
| | | | It is no longer used.
* radeon/llvm: Use a custom inserter to lower LOAD_INPUTTom Stellard2012-05-084-39/+15
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* radeon/llvm: Remove the ReorderPreloadInstructions passTom Stellard2012-05-089-100/+4
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* radeon/llvm: Remove old comment from AMDIL.hTom Stellard2012-05-081-5/+0
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* radeon/llvm: add suport for cube texturesVadim Girlin2012-05-081-1/+91
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* radeon/llvm: add support for CUBE ALU instructionVadim Girlin2012-05-085-21/+63
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* radeon/llvm: add support for some ALU instructionsVadim Girlin2012-05-084-13/+293
| | | | | | | | Add support for IABS, NOT, AND, XOR, OR, UADD, UDIV, IDIV, MOD, UMOD, INEG, I2F, U2F, F2U, F2I, USEQ, USGE, USLT, USNE, ISGE, ISLT, ROUND, MIN, MAX, IMIN, IMAX, UMIN, UMAX Signed-off-by: Vadim Girlin <[email protected]>
* radeon/llvm: add missing cases for BREAK/CONTINUEVadim Girlin2012-05-082-0/+3
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* radeon/llvm: add support for AHSR/LSHR/LSHL instructionsVadim Girlin2012-05-084-0/+53
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* radeon/llvm: add support for TXQ/TXF/DDX/DDY instructionsVadim Girlin2012-05-084-4/+39
| | | | Signed-off-by: Vadim Girlin <[email protected]>
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