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* radeon/llvm: Fix incorrect return value in SelectADDRReg()Tom Stellard2012-07-311-1/+1
* radeon/llvm: Move SMRD IMM pattern before SMRD SGPR patternTom Stellard2012-07-311-7/+6
* radeon/llvm: Cleanup AMDIL.hTom Stellard2012-07-304-91/+26
* radeon/llvm: Rename all AMDIL* classes to AMDGPU*Tom Stellard2012-07-3030-496/+496
* radeon/llvm: Merge AMDILSubtarget into AMDGPUSubtargetTom Stellard2012-07-3025-324/+156
* radeon/llvm: Merge AMDILTargetLowering class into AMDGPUTargetLoweringTom Stellard2012-07-3011-241/+144
* radeon/llvm: Remove IL_cmp DAG nodeTom Stellard2012-07-304-502/+2
* radeon/llvm: Cleanup and reorganize AMDIL .td filesTom Stellard2012-07-3013-2303/+335
* radeon/llvm: Remove lowering code for unsupported featuresTom Stellard2012-07-308-805/+50
* radeon/llvm: Remove AMDILVersion.tdTom Stellard2012-07-302-59/+0
* radeon/llvm: Remove AMDILAlgorithms.tppTom Stellard2012-07-302-94/+19
* radeon/llvm: Merge AMDILInstrInfo.cpp into AMDGPUInstrInfo.cppTom Stellard2012-07-3012-693/+512
* radeon/llvm: Merge AMDILRegisterInfo into AMDGPURegisterInfoTom Stellard2012-07-3012-283/+69
* radeon/llvm: Change the tablegen target from AMDIL to AMDGPUTom Stellard2012-07-3014-107/+119
* radeon/llvm: Add instruction defs for branches on SITom Stellard2012-07-273-17/+126
* radeon/llvm: Fix VOPC and V_CNDMASK encodingTom Stellard2012-07-274-10/+13
* radeon/llvm: Assert if we try to copy SCC regTom Stellard2012-07-271-0/+6
* radeon/llvm: Add SI DAG optimizations for setcc, select_ccTom Stellard2012-07-272-0/+54
* radeon/llvm: Add support for encoding SI branch instructionsTom Stellard2012-07-271-15/+35
* radeon/llvm: Add special nodes for SALU operations on VCCTom Stellard2012-07-276-1/+89
* radeon/llvm: Add i1 registers for SI.Tom Stellard2012-07-271-0/+2
* radeon/llvm: Fix CCReg definitions on SITom Stellard2012-07-272-3/+10
* radeon/llvm: Add bitconvert patterns for SITom Stellard2012-07-271-0/+6
* radeon/llvm: Add custom lowering for SELECT_CC nodes on SITom Stellard2012-07-272-0/+20
* radeon/llvm: Move conditional pattern leafs to common tablegen fileTom Stellard2012-07-272-41/+41
* radeon/llvm: Implement getSetCCResultType for SITom Stellard2012-07-272-0/+6
* radeon/llvm: Custom lower BR_CC for SITom Stellard2012-07-272-0/+41
* radeon/llvm: Move lowering of BR_CC node to R600ISelLoweringTom Stellard2012-07-274-31/+31
* radeon/llvm: Move lowering of SETCC node to R600ISelLoweringTom Stellard2012-07-274-38/+29
* radeon/llvm: Use correct node type when lowering SETCCTom Stellard2012-07-271-0/+1
* radeon/llvm: Move LowerSELECT_CC into R600ISelLoweringTom Stellard2012-07-274-111/+112
* radeon/llvm: Fix a bug with IF LOGICALNZ with int operandVincent Lejeune2012-07-232-3/+5
* radeon/llvm: Fix CR/LF in AMDILSIDevice.hAndreas Boll2012-07-131-1/+1
* radeon/llvm: Clean up AMDILIntrinsicInfo.cppTom Stellard2012-07-132-84/+5
* radeon/llvm: Coding style fixesTom Stellard2012-07-132-409/+325
* radeon/llvm: Don't use lp_build_swizzle_aos() for swizzlesTom Stellard2012-07-121-8/+13
* radeon/llvm: Use multiclasses for floating point loadsTom Stellard2012-07-117-50/+46
* radeon/llvm: Don't set the IMM bit in SMRD instruction definitions.Tom Stellard2012-07-111-7/+2
* radeon/llvm: Rename namespace from AMDIL to AMDGPUTom Stellard2012-07-0925-360/+361
* radeon/llvm: Enable vec4 loads on R600Tom Stellard2012-06-293-0/+20
* radeon/llvm: Enable floating point stores on R600Tom Stellard2012-06-291-0/+6
* radeon/llvm: Handle floating point loads on R600Tom Stellard2012-06-292-0/+31
* radeon/llvm: Expand UDIV and UREM nodesTom Stellard2012-06-291-4/+3
* radeon/llvm: Emit raw ISA for vertex fetch instructionsTom Stellard2012-06-292-61/+99
* radeon/llvm: Turn on the BitExtract peephole optimizationTom Stellard2012-06-212-5/+32
* radeon/llvm: Lower ROTL to BIT_ALIGNTom Stellard2012-06-216-1/+54
* radeon/llvm: Use the VLIW Scheduler for R600->NITom Stellard2012-06-2112-8/+75
* radeon/llvm: Fix CR/LF in Processors.tdTörök Edwin2012-06-191-17/+17
* radeon/llvm: Fix sin/cos codegen on R700Török Edwin2012-06-191-19/+24
* radeon/llvm: Update comment in AMDGPU.tdTom Stellard2012-06-181-2/+3