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* radeon: Move si_get_pic_param to radeon_vce.cTimur Kristóf2020-01-222-4/+4
| | | | | | Signed-off-by: Timur Kristóf <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3488>
* radeon/vcn: Handle crop parameters for encoderSatyajit Sahu2020-01-091-4/+11
| | | | | | | | | Set proper cropping parameter if frame cropping is enabled Signed-off-by: Satyajit Sahu <[email protected]> Reviewed-by: Boyuan Zhang [email protected] Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3328> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3328>
* radeonsi: preserve the scanout flag for shared resources on gfx9 and gfx10Marek Olšák2020-01-031-0/+2
| | | | | | | Closes: #2195 Closes: #2294 Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeon: Use P010 for decoding of 10-bit videosThong Thai2020-01-032-3/+6
| | | | | | | | | | | Previously, P016 was used for the decoding of 10-bit HEVC/H.265 encoded videos, which worked fine for mpv and ffmpeg. GStreamer specifically looks for P010, so this patch sets the default buffer type to P010 for HEVC decoding. Signed-off-by: Thong Thai <[email protected]> Reviewed-by: Leo Liu <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3153>
* radeon/vcn2: enable rate control for hevc encodingPierre-Eric Pelloux-Prayer2019-12-201-1/+7
| | | | | | | | | | Based on b0626c1f306 ("radeon/vcn: enable rate control for hevc encoding"). Reviewed-by: Boyuan Zhang <[email protected]> Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2225 Fixes: 587b9c5dae6 ("radeon/vcn: implement vcn 2.0 encode") Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3134> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3134>
* ac: add radeon_info::num_rings and move ring_type to amd_family.hMarek Olšák2019-11-191-13/+0
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeon/vcn: Add VP9 8K decode supportLeo Liu2019-10-301-1/+1
| | | | | | | Require increase of context buffer size Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Boyuan Zhang <[email protected]>
* util: remove LIST_DEL macroTimothy Arceri2019-10-281-3/+3
| | | | | | | Just use the inlined function directly. The macro was replaced with the function in ebe304fa540f. Reviewed-by: Eric Engestrom <[email protected]>
* util: remove LIST_ADD macroTimothy Arceri2019-10-281-3/+3
| | | | | | | Just use the inlined function directly. The macro was replaced with the function in ebe304fa540f. Reviewed-by: Eric Engestrom <[email protected]>
* util: remove LIST_ADDTAIL macroTimothy Arceri2019-10-281-1/+1
| | | | | | | Just use the inlined function directly. The macro was replaced with the function in ebe304fa540f. Reviewed-by: Eric Engestrom <[email protected]>
* util: remove LIST_INITHEAD macroTimothy Arceri2019-10-281-1/+1
| | | | | | | Just use the inlined function directly. The macro was replaced with the function in ebe304fa540f. Reviewed-by: Eric Engestrom <[email protected]>
* radeonsi: remove si_vid_join_surfaces and use combined planar allocationsMarek Olšák2019-10-092-92/+0
| | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi: fix VAAPI segfault due to various bugsMichel Dänzer2019-09-241-0/+1
| | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111236
* radeon/vcn: exclude raven2 from vcn 2.0 encode initializationIndrajit Das2019-09-131-1/+1
| | | | | Signed-off-by: Indrajit Das <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* r300,r600,radeonsi: set winsys_handle::stride,offset in drivers, not winsysesMarek Olšák2019-09-091-3/+0
| | | | Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* r300,r600,radeonsi: read winsys_handle::stride,offset in drivers, not winsysesMarek Olšák2019-09-091-3/+1
| | | | Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeon: Fix mjpeg issue for ARCTURUSZhu, James2019-09-061-0/+1
| | | | | | | ARCTURUS mjpeg is using direct register access. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Boyuan Zhang <[email protected]>
* radeon/vcn: add RENOIR VCN decode supportLeo Liu2019-09-061-4/+4
| | | | | | | It has same VCN2.x block as Navi1x Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Boyuan Zhang <[email protected]>
* radeon/vcn/vp9: add Arcturus VP9 supportLeo Liu2019-07-291-3/+3
| | | | | | | | Arcturus CHIP enum is less than Navi10, since it's still gfx9, but its VCN version belongs to VCN2.x Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeon/vcn: add Arcturus decode supportLeo Liu2019-07-291-1/+11
| | | | | | | different internal registers offset from previous HW Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeon/vcn: enable rate control for hevc encodingBoyuan Zhang2019-07-261-1/+7
| | | | | | | | | | | | | Set cu_qp_delta_enable_flag on when rate control is enabled, and set it off when rate control is disabled (e.g. constant qp). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110673 Cc: [email protected] V2: fix typo and add bugzilla info Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Leo Liu <[email protected]>
* radeon/uvd: enable rate control for hevc encodingBoyuan Zhang2019-07-261-1/+7
| | | | | | | | | | | | | Set cu_qp_delta_enable_flag on when rate control is enabled, and set it off when rate control is disabled (e.g. constant qp). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110673 Cc: [email protected] V2: fix typo and add bugzilla info Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Leo Liu <[email protected]>
* radeon/vcn: fix poc for hevc encodeBoyuan Zhang2019-07-262-2/+3
| | | | | | | | | | | | | | | | | | | MaxPicOrderCntLsb should be at least 16 according to the spec, therefore add minimum value check. Also use poc value passed from st instead of calculation in slice header encoding. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110673 Cc: [email protected] V2: Fix typo V3: Use MAX2 macro instead of coding. Also MaxPicOrderCntLsb should be power of 2 according to spec. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Leo Liu <[email protected]>
* radeon/uvd: fix poc for hevc encodeBoyuan Zhang2019-07-262-3/+3
| | | | | | | | | | | | | | | | | | | MaxPicOrderCntLsb should be at least 16 according to the spec, therefore add minimum value check. Also use poc value passed from st instead of calculation in slice header encoding. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110673 Cc: [email protected] V2: Fix typo V3: Use MAX2 macro instead of coding. Also MaxPicOrderCntLsb should be power of 2 according to spec. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Leo Liu <[email protected]>
* radeon/vcn: adding engine type for new fw interfaceBoyuan Zhang2019-07-193-2/+5
| | | | | | Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]> Acked-by: Samuel Pitoiset <[email protected]>
* radeonsi: use the correct buffer size in si_vid_clear_bufferMarek Olšák2019-07-191-1/+1
| | | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]> Acked-by: Samuel Pitoiset <[email protected]>
* radeon/vcn: update for new vcn enc interfaceBoyuan Zhang2019-07-032-1/+4
| | | | | Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeon/vcn: implement vcn 2.0 jpeg decodeBoyuan Zhang2019-07-031-56/+157
| | | | | | | Use direct register to implement vcn 2.0 jpeg deocde Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeon/vcn: add direct register boolBoyuan Zhang2019-07-032-0/+3
| | | | | | | VCN 2.0 uses direct register space where VCN 1.0 uses some indirect registers Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeon/vcn: add defines for vcn 2.0 jpegBoyuan Zhang2019-07-031-0/+25
| | | | | | | Add neccesary register defines for vcn 2.0 jpeg deocde Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeon/vcn: use variable to assign ib cmdBoyuan Zhang2019-07-033-40/+128
| | | | | Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeon/vcn: implement vcn 2.0 encodeBoyuan Zhang2019-07-034-5/+220
| | | | | Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeon/vcn: add vcn2.0 encode skeletonBoyuan Zhang2019-07-032-0/+79
| | | | | | Signed-off-by: Boyuan Zhang <[email protected]> (v2: build fix -- Nicolai) Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeon/vcn: move vcn1.0 specific defines to cBoyuan Zhang2019-07-032-29/+29
| | | | | Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeon/vcn: assign function pointer with ib functionsBoyuan Zhang2019-07-033-165/+182
| | | | | Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeon/vcn: add function pointer for ib functionsBoyuan Zhang2019-07-031-0/+32
| | | | | Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeon/vcn: move header related algorithm to vcn_encBoyuan Zhang2019-07-033-122/+142
| | | | | Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeon/vcn: move add buf func to common fileBoyuan Zhang2019-07-033-16/+17
| | | | | Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeon/vcn: move cs defines to enc header fileBoyuan Zhang2019-07-032-10/+10
| | | | | Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeon/vcn: add VP9 support for Navi10Leo Liu2019-07-031-10/+20
| | | | | | | It requires bigger DPB and context buffers Signed-off-by: Leo Liu <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeon/vcn: add VCN2 set of internal registers for IBLeo Liu2019-07-032-9/+31
| | | | | | | | From VCN2.0, the RBC have different views on the registers Signed-off-by: Leo Liu <[email protected]> (v2: rebase -- Nicolai) Acked-by: Bas Nieuwenhuizen <[email protected]>
* winsys/amdgpu: Make KMS handles valid for original DRM file descriptorMichel Dänzer2019-07-031-1/+3
| | | | | | | | | | | | | | | | | | Getting a DMA-buf fd and converting that to a handle using our duplicate of that file descriptor (getting at which requires passing a radeon_winsys pointer to the buffer_get_handle hook) makes sure of this, since duplicated file descriptors reference the same file description and therefore the same GEM handle namespace. This is necessary because libdrm_amdgpu may use a different DRM file descriptor with a separate handle namespace internally, e.g. because it always reuses any existing amdgpu_device_handle for the same device. amdgpu_bo_export returns a handle which is valid for that internal file descriptor. Bugzilla: https://bugs.freedesktop.org/110903 Reviewed-by: Marek Olšák <[email protected]> Tested-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeon/uvd: fix calc_ctx_size_h265_main10Pierre-Eric Pelloux-Prayer2019-06-282-6/+6
| | | | | | | | | | | Left shift was applied twice. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110702 Reviewed-by: Leo Liu <[email protected]> Tested-by: <[email protected]> Signed-off-by: Marek Olšák <[email protected]> Cc: <[email protected]>
* ac: add radeon_info::is_amdgpu instead of checking drm_major == 3Marek Olšák2019-06-142-4/+4
| | | | | | and clean up Reviewed-by: Samuel Pitoiset <[email protected]>
* r600+radeonsi: use ctx_query_reset_status on radeonMarek Olšák2019-05-161-1/+0
| | | | This allows a nice cleanup, because the winsys always handles it.
* winsys/amdgpu: add REWIND emulation via INDIRECT_BUFFER into cs_check_spaceMarek Olšák2019-05-161-1/+5
| | | | Acked-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: add a parallel compute IB coupled with a gfx IBMarek Olšák2019-05-161-1/+31
| | | | | Tested-by: Dieter Nützel <[email protected]> Acked-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: make IBs writable and expose their addressMarek Olšák2019-04-231-0/+1
| | | | | Tested-by: Dieter Nützel <[email protected]> Acked-by: Nicolai Hähnle <[email protected]>
* ac: add radeon_info::marketing_name, replacing the winsys callbackMarek Olšák2019-04-231-2/+0
| | | | | Tested-by: Dieter Nützel <[email protected]> Acked-by: Nicolai Hähnle <[email protected]>
* radeon/vce:Add support for frame_cropping_flag of ↵suresh guttula2019-04-161-2/+9
| | | | | | | | | | | | | | VAEncSequenceParameterBufferH264 This patch will add support for frame_cropping when the input size is not matched with aligned size. Currently vaapi driver ignores frame cropping values provided by client. This change will update SPS nalu with proper cropping values. v2: Moving default crop setting to else when enc_frame_cropping_flag is not set. Signed-off-by: Satyajit Sahu <[email protected]> Reviewed-by: Leo Liu <[email protected]>
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