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* radeon/llvm: Match fexp2 for SI.Michel Dänzer2012-09-071-1/+3
* radeon/llvm: Add intrinsic for enabling whole quad mode in SI pixel shaders.Michel Dänzer2012-09-064-0/+23
* radeon/llvm: SI shader vector instructions implicitly use the EXEC register.Michel Dänzer2012-09-061-0/+4
* radeon/llvm: Extend SI EXEC register support.Michel Dänzer2012-09-062-2/+7
* radeon/llvm: Remove R600InstrInfo.td from TD_FILESTom Stellard2012-09-061-1/+0
* radeon/llvm: Cleanup makefileTom Stellard2012-09-062-13/+37
* radeon/llvm: Fix operand ordering for V_CNDMASK_B32Tom Stellard2012-09-051-3/+3
* radeon/llvm: Use correct float->int conversion opcode on SI.Tom Stellard2012-09-051-2/+4
* radeon/llvm: Fix lowering of SI_V_CNDLTTom Stellard2012-09-041-3/+3
* radeon/llvm: Fix encoding of V_CNDMASK_B32Tom Stellard2012-09-042-4/+4
* radeon/llvm: do not convert f32 operand of select_cc nodeVincent Lejeune2012-09-041-20/+20
* radeon/llvm: custom lowering for FP_TO_UINT when dst is i1 (bool)Vincent Lejeune2012-09-042-2/+26
* radeon/llvm: support setcc on f32Vincent Lejeune2012-09-041-9/+27
* radon/llvm: br_cc f32 now lowered without castVincent Lejeune2012-09-041-9/+24
* radeon/llvm: swap wrong OPCODE_IS_*_ZERO_* opcode and useVincent Lejeune2012-09-042-4/+4
* radeon/llvm: fix SelectADDR8BitOffsetChristian König2012-09-041-1/+1
* radeon/llvm: Rework how immediate operands are handled with SITom Stellard2012-08-3110-44/+150
* radeon/llvm: Fix typo in assertTom Stellard2012-08-311-1/+1
* radeon/llvm: Fix isEG tablegen predicateTom Stellard2012-08-311-3/+5
* radeon/llvm: Add support for RCP instruction on SITom Stellard2012-08-311-1/+3
* radeon/llvm: Support AMDGPUfmin DAG node on SITom Stellard2012-08-311-1/+3
* radeon/llvm: Fix encoding of FP immediates on SITom Stellard2012-08-291-1/+6
* radeon/llvm: Create a register class for the M0 registerTom Stellard2012-08-295-16/+24
* radeon/llvm: Set the neverHasSideEffects bit on more instructionsTom Stellard2012-08-291-0/+2
* radeon/llvm: Declare the interpolation intrinsics as ReadOnlyTom Stellard2012-08-292-1/+2
* radeon/llvm: Mark M0 as a def when lowering interpolation instructionsTom Stellard2012-08-291-4/+2
* radeon/llvm: Handle TGSI KIL opcode for SI.Michel Dänzer2012-08-283-0/+44
* radeon/llvm: Basic support for SI EXEC register.Michel Dänzer2012-08-283-2/+23
* radeonsi: Use FP16 shader export format when necessary / possible.Michel Dänzer2012-08-272-1/+4
* radeon/llvm: Cleanup R600Instructions.tdTom Stellard2012-08-242-93/+28
* radeon/llvm: Set End of Program bit on RAT instructionsTom Stellard2012-08-233-10/+14
* radeon/llvm: Use correct instruction for moving immediatesTom Stellard2012-08-231-1/+2
* radeon/llvm: Fix some coding style issuesTom Stellard2012-08-2314-82/+135
* radeon/llvm: Pull changes from external version of the backendTom Stellard2012-08-2321-76/+38
* radeon/llvm: Simplify the convert to ISA passTom Stellard2012-08-233-20/+7
* radeon/llvm: Make sure to use the Text section in the AsmPrinterTom Stellard2012-08-231-0/+2
* radeon/llvm: Use the MCCodeEmitter for R600Tom Stellard2012-08-2316-738/+779
* radeon/llvm: Use the MCCodeEmitter for SITom Stellard2012-08-2315-431/+591
* radeon/llvm: Set 64BitPtr feature bit for SITom Stellard2012-08-231-1/+1
* radeon/llvm: Lower RETFLAG DAG Node to S_ENDPGM on SITom Stellard2012-08-233-8/+12
* radeon/llvm: Add AsmPrinterTom Stellard2012-08-238-0/+193
* radeon/llvm: Mark JUMP as a pseudo instructionTom Stellard2012-08-231-1/+1
* radeon/llvm: Remove the last uses of MachineOperand flagsTom Stellard2012-08-232-8/+27
* radeon/llvm: Add flag operand to some instructionsTom Stellard2012-08-237-33/+97
* radeon/llvm: Encapsulate setting of MachineOperand flagsTom Stellard2012-08-234-50/+71
* radeon/llvm: ExpandSpecialInstrs - Add support for cube instructionsTom Stellard2012-08-214-63/+100
* radeon/llvm: ExpandSpecialInstrs - Add support for vector instructionsTom Stellard2012-08-212-15/+30
* radeon/llvm: Add R600ExpandSpecialInstrs passTom Stellard2012-08-216-14/+112
* radeon/llvm: Add helper function for getting sub reg indicesTom Stellard2012-08-213-6/+19
* radeon-llvm: Start multithreaded before using llvm.Mathias Fröhlich2012-08-201-0/+15
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