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path: root/src/gallium/drivers/radeon
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* radeon/llvm: replace shader type intrinsic with function attributeChristian König2013-03-072-0/+24
* radeon/llvm: fix trivial warningsChristian König2013-03-061-4/+3
* radeon/llvm: Remove stale comment about radeon_llvm_emit_prepare_cube_coordsMichel Dänzer2013-02-221-1/+0
* radeon/llvm: Fix build with LLVM 3.3Tom Stellard2013-02-191-1/+8
* r600g/llvm: Set Inputs/Outputs count to 32 (api reported value)Vincent Lejeune2013-02-181-2/+2
* r600g/llvm: Fix alpha_to_one piglit testsVincent Lejeune2013-02-181-0/+1
* r600g/llvm: Add support for UBOVincent Lejeune2013-02-181-0/+17
* radeonsi: Adapt to sample intrinsics changes.Michel Dänzer2013-02-042-27/+25
* r600g: improve inputs/interpolation handling with llvm backendVadim Girlin2013-01-281-2/+1
* radeon/llvm: Handle LP_CHAN_ALL in emit_fetch_immediate().Michel Dänzer2013-01-221-1/+11
* r600g/llvm: tgsi to llvm emits store.swizzle intrinsic for vs/fs outputVincent Lejeune2013-01-181-0/+1
* r600g/llvm: tgsi to llvm emits stream output intrinsics.Vincent Lejeune2013-01-181-0/+1
* r600g/llvm:translate ARL opcode to a simple castVincent Lejeune2013-01-181-2/+12
* r600g/llvm: rework handling of the constantsVadim Girlin2013-01-181-0/+4
* drivers/radeon: Don't link against libgallium.laTom Stellard2013-01-111-2/+1
* radeon/llvm: Convert to AutomakeTom Stellard2013-01-103-17/+33
* radeon/llvm: Remove backend code from MesaTom Stellard2013-01-0499-19168/+0
* Support LLVM >= 3.2 on radeonsi and opencl.Johannes Obermayr2013-01-041-0/+7
* radeon/llvm: improve cube map handlingVadim Girlin2012-12-182-20/+69
* radeon/llvm: fix TXQ_LZ handling for cube mapsVadim Girlin2012-12-181-2/+4
* radeon/llvm: Export prepare_cube_coords helper to driver.Michel Dänzer2012-12-062-8/+13
* r600g: use default action for min/max opcode in tgsi to llvmVincent Lejeune2012-12-051-4/+0
* r600g: use default action for fdiv/rcp opcodeVincent Lejeune2012-12-051-6/+1
* r600g: Use default mul/mad function for tgsi-to-llvmVincent Lejeune2012-12-051-8/+4
* r600g: make tgsi-to-llvm generates store.pixel* intrinsic for fsVincent Lejeune2012-11-021-0/+3
* radeon/llvm: Add intrinsic for reading SI FRONT_FACE VGPR in the pixel shader.Michel Dänzer2012-10-262-0/+6
* radeon/llvm: Sort tgsi opcode action initializationTom Stellard2012-10-191-59/+50
* radeon/llvm: Fix lowering TGSI_OPCODE_SSGTom Stellard2012-10-191-1/+1
* radeon/llvm: Fix build with LLVM 3.2Tom Stellard2012-10-111-3/+10
* radeon/llvm: use ceil intrinsic instead of llvm.AMDIL.round.posinfVincent Lejeune2012-10-103-6/+2
* radeon/llvm: use floor intrinsic instead of llvm.AMDIL.floorVincent Lejeune2012-10-105-5/+5
* radeon/llvm: use llvm fabs intrinsicVincent Lejeune2012-10-103-6/+4
* radeon/llvm: use llvm intrinsic for flog2Vincent Lejeune2012-10-104-5/+4
* radeon/llvm: add support for cos/sin intrinsicVincent Lejeune2012-10-103-12/+15
* radeon/llvm: add a pattern for fsqrtVincent Lejeune2012-10-101-0/+3
* radeon/llvm: Disable SI flow control again for now.Michel Dänzer2012-10-021-1/+2
* radeon/llvm: Only initialize the AMDGPU targetTom Stellard2012-10-011-7/+1
* radeon: Fix build with LLVM 3.1Tom Stellard2012-10-011-0/+1
* radeon: Support LLVM 3.2Tom Stellard2012-10-013-3/+11
* r600g: add some members to radeon_llvm_contextVincent Lejeune2012-09-281-0/+6
* radeon/llvm: improve select_cc lowering to generate CND* more oftenVincent Lejeune2012-09-273-41/+88
* radeon/llvm: Fix instruction encoding for r600 family GPUsTom Stellard2012-09-243-15/+14
* radeon/llvm: support for interpolation intrinsicsVincent Lejeune2012-09-2210-2/+318
* radeon/llvm: Handle loads from the constants address space.Tom Stellard2012-09-212-0/+10
* radeon/llvm: Add support for v4f32 stores on R600Tom Stellard2012-09-213-9/+27
* radeon/llvm: Add support for i8 reads on R600Tom Stellard2012-09-213-0/+25
* radeon/llvm: Expand vector fadd and fmul on R600Tom Stellard2012-09-211-0/+3
* radeon/llvm: Add optimization for FP_ROUNDTom Stellard2012-09-212-0/+27
* radeon/llvm: Replace AMDGPU pow intrinsic with the llvm versionTom Stellard2012-09-214-7/+26
* radeon/llvm: Emit ISA for ALU instructions in the R600 code emitterMichal Sciubidlo2012-09-195-139/+238
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