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* radeon/uvd: fix VC-1 simple/main profile decode v2Boyuan Zhang2015-11-062-2/+7
| | | | | | | | | | | We just needed to set the extra width/height fields to get this working. v2 (chk): rebased, CC stable added, commit message added, fixed coding style Signed-off-by: Boyuan Zhang <[email protected]> Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Cc: "10.6 11.0" <[email protected]>
* gallium/radeon: allow returning SDMA fences from pipe->flushMarek Olšák2015-11-041-8/+56
| | | | | | | pipe->flush never returned SDMA fences. This fixes it. This is only an issue on amdgpu where fences can signal out of order. Reviewed-by: Michel Dänzer <[email protected]>
* gallium/radeon: always return the last SDMA fence on SDMA flush if neededMarek Olšák2015-11-042-4/+8
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeon/uvd: implement and add flag for VAAPI HEVC decodeBoyuan Zhang2015-10-272-0/+16
| | | | | | Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* winsys/amdgpu: remove the dcc_enable surface flagMarek Olšák2015-10-272-3/+1
| | | | | | dcc_size is sufficient and doesn't need a further comment in my opinion. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add debug flags that disable DCC and DCC fast clearMarek Olšák2015-10-273-0/+10
| | | | | | | For debugging, bug reports, etc. This is not in the radeonsi directory, but it is about radeonsi. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: properly check if DCC is enabled and allocatedMarek Olšák2015-10-271-1/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: Implement DCC fast clear.Bas Nieuwenhuizen2015-10-241-11/+96
| | | | | | | | | | | Uses the DCC buffer instead of the CMASK buffer. The ELIMINATE_FAST_CLEAR still works. Furthermore, with DCC compression we can directly clear to a limited set of colors such that we do not need a postprocessing step. v2 Marek: check dcc_buffer && dirty_level_mask in set_sampler_view Signed-off-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeonsi: Enable DCC.Bas Nieuwenhuizen2015-10-243-0/+4
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeonsi: Disable operations that do not work with DCC.Bas Nieuwenhuizen2015-10-241-0/+5
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeonsi: Allocate buffers for DCC.Bas Nieuwenhuizen2015-10-244-0/+50
| | | | | | | | | | | As the alignment requirements can be 32 KiB or more, also adding an aligned buffer creation function. DCC is disabled for textures that can be shared as sharing the DCC buffers has not been implemented yet. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeonsi: add support for Stoney asics (v3)Samuel Li2015-10-232-0/+7
| | | | | | | | | | | v2 (agd): rebase on mesa master, split pci ids to separate commit v3 (agd): use carrizo for llvm processor name for llvm 3.7 and older Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Samuel Li <[email protected]> Cc: [email protected]
* radeon/uvd: don't expose HEVC on old UVD hw (v3)Alex Deucher2015-10-221-32/+18
| | | | | | | | | | | | | | | | The section for UVD 2 and older was not updated when HEVC support was added. Reported by Kano on irc. v2: integrate the UVD2 and older checks into the main switch statement. v3: handle encode checking as well. Encode is already checked in the top case statement, so drop encode checks in the lower case statement. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
* radeonsi: don't use the AMDGPU intrinsic for CMPMarek Olšák2015-10-171-9/+22
| | | | | | | No difference according to shader-db. Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeonsi: use LRP from gallivmMarek Olšák2015-10-171-2/+0
| | | | | | | | | | | | | | | | | | Totals: SGPRS: 344552 -> 344368 (-0.05 %) VGPRS: 197132 -> 197552 (0.21 %) Code Size: 7375376 -> 7366304 (-0.12 %) bytes LDS: 91 -> 91 (0.00 %) blocks Scratch: 1679360 -> 1615872 (-3.78 %) bytes per wave Totals from affected shaders: SGPRS: 47736 -> 47552 (-0.39 %) VGPRS: 27952 -> 28372 (1.50 %) Code Size: 1392724 -> 1383652 (-0.65 %) bytes LDS: 39 -> 39 (0.00 %) blocks Scratch: 513024 -> 449536 (-12.38 %) bytes per wave Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: don't emit AMDGPU intrinsics for integer abs, min, maxMarek Olšák2015-10-171-10/+50
| | | | | | | No difference according to shader-db. (with the new S_ABS_I32 pattern) Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeonsi: don't emit AMDGPU intrinsics for EX2, ROUND, TRUNCMarek Olšák2015-10-171-3/+3
| | | | | | | No difference according to shader-db. Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeonsi: initialize output, temp, and address registers to "undef"Marek Olšák2015-10-171-4/+15
| | | | | | | | | | | | | | | | | | | | | This removes "v_mov v0, 0" which typically occurs before exports. Totals: SGPRS: 345216 -> 344552 (-0.19 %) VGPRS: 197684 -> 197132 (-0.28 %) Code Size: 7390408 -> 7375376 (-0.20 %) bytes LDS: 91 -> 91 (0.00 %) blocks Scratch: 1842176 -> 1679360 (-8.84 %) bytes per wave Totals from affected shaders: SGPRS: 101336 -> 100672 (-0.66 %) VGPRS: 53920 -> 53368 (-1.02 %) Code Size: 2170176 -> 2155144 (-0.69 %) bytes LDS: 2 -> 2 (0.00 %) blocks Scratch: 1015808 -> 852992 (-16.03 %) bytes per wave Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* gallium/radeon: add separate stencil level dirty flagsMarek Olšák2015-10-031-0/+1
| | | | | | | We will only do depth-only or stencil-only decompress blits, whichever is needed by textures, instead of always doing both. Reviewed-by: Michel Dänzer <[email protected]>
* winsys/amdgpu: add winsys function cs_get_buffer_listMarek Olšák2015-10-031-0/+16
| | | | | | For debugging. Reviewed-by: Michel Dänzer <[email protected]>
* gallium/radeon: stop using "reloc" in a few placesMarek Olšák2015-10-034-15/+14
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* gallium/radeon: tell the winsys the exact resource binding typesMarek Olšák2015-10-036-23/+75
| | | | | | | Use the priority flags and expand them. This information will be used for debugging. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: add an option for debugging VM faultsMarek Olšák2015-10-032-0/+2
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeon/llvm: Initialize gallivm targets when initializing the AMDGPU target v2Tom Stellard2015-10-021-0/+2
| | | | | | | | | | | | | | This fixes a race condition in the glx-multithreaded-shader-compile test. v2: - Replace gallivm_init_llvm_{begin,end}() with gallivm_init_llvm_targets(). Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Mathias Fröhlich <[email protected]> Reviewed-by: Emil Velikov <[email protected]> CC: "10.6 11.0" <[email protected]>
* gallium/radeon: Use call_once() when initailizing LLVM targetsTom Stellard2015-10-021-13/+12
| | | | | | | | Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Mathias Fröhlich <[email protected]> Reviewed-by: Emil Velikov <[email protected]> CC: "10.6 11.0" <[email protected]>
* radeon/vce: fix vui time_scale zero errorLeo Liu2015-09-251-0/+3
| | | | | | | | | if app pass 0 as frame_rate_num, it should not be encoded to the VUI. Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Cc: "10.6 11.0" <[email protected]>
* gallium/radeon: remove the percentage symbol from HUD temperatureBenjamin Bellec2015-09-241-1/+1
| | | | | | | The HUD adds '%' if max == 100. Signed-off-by: Benjamin Bellec <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* gallium/radeon: add a fail path for depth MSAA texture readbackMarek Olšák2015-09-241-0/+5
| | | | | | Cc: 11.0 <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* gallium/radeon: handle buffer alloc failures in r600_draw_rectangleMarek Olšák2015-09-241-0/+3
| | | | | | Cc: 11.0 <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* gallium/radeon: handle buffer_map staging buffer failures betterMarek Olšák2015-09-241-4/+3
| | | | | | Cc: 11.0 <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* gallium/radeon: handle PIPE_TRANSFER_FLUSH_EXPLICITMarek Olšák2015-09-103-22/+44
| | | | | | | | Basically, do the same thing as for buffer_unmap, but use the explicit range instead. It's for apps which want to map a whole buffer and mark touched ranges explicitly. Reviewed-by: Michel Dänzer <[email protected]>
* gallium/radeon: drop support for LLVM 3.4Marek Olšák2015-09-103-12/+1
| | | | | | This allows using the new tex instrinsics unconditionally. Reviewed-by: Michel Dänzer <[email protected]>
* gallium/radeon: remove 'dirty' member from r600_atomGrazvydas Ignotas2015-09-031-2/+1
| | | | | | It's no longer used by both r600 and radeonsi now. Signed-off-by: Marek Olšák <[email protected]>
* winsys/radeon: add a flag telling how gfx IBs should be paddedMarek Olšák2015-09-011-0/+1
| | | | | | | This is always false on amdgpu (set by calloc). Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]>
* gallium/radeon: rename r600_context_bo_reloc -> radeon_add_to_buffer_listMarek Olšák2015-09-011-6/+16
| | | | | | | this name should be easy to understand without other knowledge Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]>
* gallium/radeon: rename write_*_reg functionsMarek Olšák2015-09-013-37/+37
| | | | | | | | e.g. radeon_set_context_reg is nicer and looks consistent next to radeon_emit(). Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]>
* radeonsi: avoid redundant CB and DB register updatesMarek Olšák2015-09-012-2/+4
| | | | | | | | | | The main idea is to avoid setting CB_COLORi_INFO = 0 for i>0 repeatedly when those colorbuffers aren't used. This is mainly for glamor. Same for DB. Z_INFO and STENCIL_INFO need to be cleared only once. Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]>
* radeonsi: remove no-op 32-bit maskingMarek Olšák2015-08-291-2/+2
| | | | Reviewed-by: Alex Deucher <[email protected]>
* gallium/radeon: fix the ADDRESS_HI mask for EVENT_WRITE CIK packetsMarek Olšák2015-08-291-8/+8
| | | | | Cc: [email protected] Reviewed-by: Alex Deucher <[email protected]>
* gallium/radeon: read_registers should return bool meaning success or failureMarek Olšák2015-08-261-1/+1
| | | | | Acked-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]>
* radeon/uvd: remove unused variablesGrazvydas Ignotas2015-08-181-4/+1
| | | | | | Recent commits introduced new unused variable warnings, fix them. Reviewed-by: Christian König <[email protected]>
* radeon/uvd: implement HEVC supportBoyuan Zhang2015-08-143-17/+298
| | | | | | | | | | | | | add context buffer to fix H265 uvd decode issue. fix H265 corruption issue caused by incorrect assigned ref_pic_list. v2: disable interlace for HEVC add CZ sps flag workaround fix coding style Signed-off-by: Christian König <[email protected]> Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* radeon/vce: disable VCE dual instance for harvest partLeo Liu2015-08-142-1/+4
| | | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/vce: implement VCE dual instance supportLeo Liu2015-08-143-5/+30
| | | | | | | | | | VCE dual instances are encoding in parallel, it needs two frames for encoding with their own parameters in one IB. Master instance will check the task info to find another frame, assign it to the slave instance Signed-off-by: Leo Liu <[email protected]> Signed-off-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]>
* radeon/video: config encode stacked frame number based on HWLeo Liu2015-08-141-0/+2
| | | | | | | | since VCE 3.0 with dual instances, we need stack frames for them. Signed-off-by: Leo Liu <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/vce: make reloc offset signedChristian König2015-08-144-6/+6
| | | | | | | We need a negative offset for FW 50. Signed-off-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]>
* radeon/vce: add config task and put task info into encoder v2Leo Liu2015-08-144-33/+47
| | | | | | | | | | | The config task has own task ID, extract the configuration functions into config task. v2 (chk): calculate offset automatically Signed-off-by: Leo Liu <[email protected]> Signed-off-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]>
* radeon/vce: fix VCE fail after rebaseLeo Liu2015-08-141-8/+6
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/vce: add dual pipe support for VILeo Liu2015-08-144-22/+21
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/vce: add new firmware support for VI and CILeo Liu2015-08-141-1/+7
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
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