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* gallium/radeon: remove DBG_TEXMIPMarek Olšák2015-12-033-4/+2
| | | | | | we don't need 2 flags for dumping texture info Reviewed-by: Michel Dänzer <[email protected]>
* radeon: only suspend queries on flush if they haven't been suspended yetNicolai Hähnle2015-11-282-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | Non-timer queries are suspended during blits. When the blits end, the queries are resumed, but this resume operation itself might run out of CS space and trigger a flush. When this happens, we must prevent a duplicate suspend during preflush suspend, and we must also prevent a duplicate resume when the CS flush returns back to the original resume operation. This fixes a regression that was introduced by: commit 8a125afa6e88a3eeddba8c7fdc1a75c9b99d5489 Author: Nicolai Hähnle <[email protected]> Date: Wed Nov 18 18:40:22 2015 +0100 radeon: ensure that timing/profiling queries are suspended on flush The queries_suspended_for_flush flag is redundant because suspended queries are not removed from their respective linked list. Reviewed-by: Marek Olšák <[email protected]> Reported-by: Axel Davy <[email protected]> Cc: "11.1" <[email protected]> Tested-by: Axel Davy <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeon: use PIPE_DRIVER_QUERY_FLAG_DONT_LIST for perfcountersNicolai Hähnle2015-11-261-0/+2
| | | | | | | | Since the query names are not very enlightening, and there are thousands of them, GALLIUM_HUD=help should only show the first and last query name for each hardware block. Reviewed-by: Marek Olšák <[email protected]>
* radeon: delay the generation of driver query names until first useNicolai Hähnle2015-11-262-96/+106
| | | | | | | This shaves a bit more time off the startup of programs that don't actually use performance counters. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: implement AMD_performance_monitor for CIK+Nicolai Hähnle2015-11-256-3/+784
| | | | | | | | | | | | | | | | | | Expose most of the performance counter groups that are exposed by Catalyst. Ideally, the driver will work with GPUPerfStudio at some point, but we are not quite there yet. In any case, this is the reason for grouping multiple instances of hardware blocks in the way it is implemented. The counters can also be shown using the Gallium HUD. If one is interested to see how work is distributed across multiple shader engines, one can set the environment variable RADEON_PC_SEPARATE_SE=1 to obtain finer-grained performance counter groups. Part of the implementation is in radeon because an implementation for older hardware would largely follow along the same lines, but exposing a different set of blocks which are programmed slightly differently. Reviewed-by: Marek Olšák <[email protected]>
* radeon: scale query buffer size to result sizeNicolai Hähnle2015-11-251-1/+1
| | | | | | | Performance monitor queries can become very big, especially considering that instances of a block in different shader engines are queried separately. Reviewed-by: Marek Olšák <[email protected]>
* radeon: extend CIK_UCONFIG_REG_END for performance countersNicolai Hähnle2015-11-251-1/+1
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeon: add perfcounter-related EVENT_TYPEsNicolai Hähnle2015-11-251-0/+3
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeon: additional constants for WAIT_REG_MEM and EVENT_WRITE_EOPNicolai Hähnle2015-11-251-0/+8
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeon/llvm: Use llvm.AMDIL.exp intrinsic again for nowMichel Dänzer2015-11-241-1/+1
| | | | | | | | llvm.exp2.f32 doesn't work in some cases yet. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92709 Reviewed-by: Nicolai Hähnle <[email protected]>
* radeon/uvd: uv pitch separation for stoneyBoyuan Zhang2015-11-232-1/+6
| | | | | | | | v2: set the behaviour default for future ASICs. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]> Cc: [email protected]
* radeon: re-prepare query buffers on begin_query for predicate queriesNicolai Hähnle2015-11-202-15/+18
| | | | | | | | | | | | | | | | The point of prepare_buffer is to ensure that the query buffer contains valid initial data for conditional rendering: as long as the buffer is initialized correctly, the GPU is able to tell whether query results have been written already (and wait or fall back to unconditional rendering if desired). This means prepare_buffer needs to be called again when a buffer is reused. Conversely, for queries that cannot be used for conditional rendering (notably pipeline statistics), we can re-use buffers immediately, and they do not need to be initialized. Reviewed-by: Marek Olšák <[email protected]> Tested-by: Andy Furniss <[email protected]>
* radeon: reset query buffers for PIPE_QUERY_TIMESTAMPNicolai Hähnle2015-11-201-8/+18
| | | | | | | | | | Since begin_query is not called for this query type, we need to reset the query buffer state in end_query instead. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93015 Reviewed-by: Marek Olšák <[email protected]> Tested-by: Andy Furniss <[email protected]> Tested-by: Mathias Tillman <[email protected]>
* radeon/vce: disable two pipe mode for stoneyLeo Liu2015-11-201-1/+2
| | | | | | | | Only one encoding pipe available for Stoney Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/vce: add new firmware interface supportLeo Liu2015-11-204-5/+262
| | | | | | | | Add new interface to create and encode Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon: ensure that timing/profiling queries are suspended on flushNicolai Hähnle2015-11-202-9/+6
| | | | | | | The queries_suspended_for_flush flag is redundant because suspended queries are not removed from their respective linked list. Reviewed-by: Marek Olšák <[email protected]>
* radeon: count cs dwords separately for query begin and endNicolai Hähnle2015-11-182-15/+21
| | | | | | This will be important for perfcounter queries. Reviewed-by: Marek Olšák <[email protected]>
* radeon: expose r600_query_hw functions for reuseNicolai Hähnle2015-11-182-14/+27
| | | | | Reviewed-by: Marek Olšák <[email protected]> [Fixed a rebase conflict and re-tested before pushing.]
* radeon: implement r600_query_hw_get_result via function pointersNicolai Hähnle2015-11-182-99/+94
| | | | | | We will need the clear_result override for the batch query implementation. Reviewed-by: Marek Olšák <[email protected]>
* radeon: split hw query buffer handling from cs emitNicolai Hähnle2015-11-182-81/+133
| | | | | | | | | The idea here is that driver queries implemented outside of common code will use the same query buffer handling with different logic for starting and stopping the corresponding counters. Reviewed-by: Marek Olšák <[email protected]> [Fixed a rebase conflict and re-tested before pushing.]
* radeon: convert hardware queries to the new styleNicolai Hähnle2015-11-182-148/+172
| | | | | | | | | Move r600_query and r600_query_hw into the header because we will want to reuse the buffer handling and suspend/resume logic outside of the common radeon code. Reviewed-by: Marek Olšák <[email protected]> [Fixed a rebase conflict and re-tested before pushing.]
* radeon: convert software queries to the new styleNicolai Hähnle2015-11-181-172/+194
| | | | | | | | Software queries are all queries that do not require suspend/resume and explicit handling of result buffers. Reviewed-by: Marek Olšák <[email protected]> [Fixed a rebase conflict and re-tested before pushing.]
* radeon: add query handler function pointersNicolai Hähnle2015-11-182-7/+62
| | | | | | | | The goal here is to be able to move the implementation details of hardware- specific queries (in particular, performance counters) out of the common code. Reviewed-by: Marek Olšák <[email protected]> [Fixed a rebase conflict and re-tested before pushing.]
* radeon: move R600_QUERY_* constants into a new query header fileNicolai Hähnle2015-11-184-15/+51
| | | | | | | More query-related structures will have to be moved into their own header file to support hardware-specific performance counters. Reviewed-by: Marek Olšák <[email protected]>
* radeon: cleanup driver query listNicolai Hähnle2015-11-181-29/+55
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeon: move get_driver_query_info to r600_query.cNicolai Hähnle2015-11-183-45/+51
| | | | Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: shorten render_cond variable namesMarek Olšák2015-11-133-11/+11
| | | | | | and ..._cond -> ..._invert Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: remove predicate_drawing flagMarek Olšák2015-11-132-2/+0
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: atomize render condition (SET_PREDICATION)Marek Olšák2015-11-133-44/+38
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: simplify restoring render condition after flushMarek Olšák2015-11-132-21/+5
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: don't use PREDICATION_OP_CLEARMarek Olšák2015-11-131-36/+24
| | | | | | Not setting the predication bit is sufficient. Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: simplify disabling render condition for u_blitterMarek Olšák2015-11-131-1/+2
| | | | | | just disable it by not setting the predication bit Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: inline the r600_rings structureMarek Olšák2015-11-135-56/+52
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: remove the IB flushing flagMarek Olšák2015-11-132-8/+2
| | | | | | | Not needed anymore. A similar flag will be introduced in the next commit, which will be private in radeonsi. Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: move GFX/DMA flushing from add_to_buffer_list to need_cs_spaceMarek Olšák2015-11-132-15/+4
| | | | | | | | need_cs_space isn't invoked so often and is called before all commands too. This is a lot cleaner. The code in radeon_add_to_buffer_list always seemed dodgy to me. Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: fix PIPE_QUERY_GPU_FINISHEDMarek Olšák2015-11-131-1/+1
| | | | | | | | | Broken by the addition of r600_multi_fence in 3b37155a68acc351cba86a1fa142bd0de2192d4c Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89014 Reviewed-by: Michel Dänzer <[email protected]>
* radeon/uvd: fix VC-1 simple/main profile decode v2Boyuan Zhang2015-11-062-2/+7
| | | | | | | | | | | We just needed to set the extra width/height fields to get this working. v2 (chk): rebased, CC stable added, commit message added, fixed coding style Signed-off-by: Boyuan Zhang <[email protected]> Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Cc: "10.6 11.0" <[email protected]>
* gallium/radeon: allow returning SDMA fences from pipe->flushMarek Olšák2015-11-041-8/+56
| | | | | | | pipe->flush never returned SDMA fences. This fixes it. This is only an issue on amdgpu where fences can signal out of order. Reviewed-by: Michel Dänzer <[email protected]>
* gallium/radeon: always return the last SDMA fence on SDMA flush if neededMarek Olšák2015-11-042-4/+8
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeon/uvd: implement and add flag for VAAPI HEVC decodeBoyuan Zhang2015-10-272-0/+16
| | | | | | Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* winsys/amdgpu: remove the dcc_enable surface flagMarek Olšák2015-10-272-3/+1
| | | | | | dcc_size is sufficient and doesn't need a further comment in my opinion. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add debug flags that disable DCC and DCC fast clearMarek Olšák2015-10-273-0/+10
| | | | | | | For debugging, bug reports, etc. This is not in the radeonsi directory, but it is about radeonsi. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: properly check if DCC is enabled and allocatedMarek Olšák2015-10-271-1/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: Implement DCC fast clear.Bas Nieuwenhuizen2015-10-241-11/+96
| | | | | | | | | | | Uses the DCC buffer instead of the CMASK buffer. The ELIMINATE_FAST_CLEAR still works. Furthermore, with DCC compression we can directly clear to a limited set of colors such that we do not need a postprocessing step. v2 Marek: check dcc_buffer && dirty_level_mask in set_sampler_view Signed-off-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeonsi: Enable DCC.Bas Nieuwenhuizen2015-10-243-0/+4
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeonsi: Disable operations that do not work with DCC.Bas Nieuwenhuizen2015-10-241-0/+5
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeonsi: Allocate buffers for DCC.Bas Nieuwenhuizen2015-10-244-0/+50
| | | | | | | | | | | As the alignment requirements can be 32 KiB or more, also adding an aligned buffer creation function. DCC is disabled for textures that can be shared as sharing the DCC buffers has not been implemented yet. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeonsi: add support for Stoney asics (v3)Samuel Li2015-10-232-0/+7
| | | | | | | | | | | v2 (agd): rebase on mesa master, split pci ids to separate commit v3 (agd): use carrizo for llvm processor name for llvm 3.7 and older Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Samuel Li <[email protected]> Cc: [email protected]
* radeon/uvd: don't expose HEVC on old UVD hw (v3)Alex Deucher2015-10-221-32/+18
| | | | | | | | | | | | | | | | The section for UVD 2 and older was not updated when HEVC support was added. Reported by Kano on irc. v2: integrate the UVD2 and older checks into the main switch statement. v3: handle encode checking as well. Encode is already checked in the top case statement, so drop encode checks in the lower case statement. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
* radeonsi: don't use the AMDGPU intrinsic for CMPMarek Olšák2015-10-171-9/+22
| | | | | | | No difference according to shader-db. Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
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