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drivers
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radeon
Commit message (
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Author
Age
Files
Lines
*
radeon/llvm: Add support for fp_to_sint on SI
Tom Stellard
2012-08-02
1
-1
/
+3
*
radeon/llvm: Remove CMOVLOG DAG node
Tom Stellard
2012-08-02
6
-75
/
+9
*
radeonsi: Handle TGSI DIV opcode.
Michel Dänzer
2012-08-02
1
-0
/
+5
*
radeon/llvm: fix fp immediates on SI
Christian König
2012-08-02
1
-7
/
+20
*
radeon/llvm: fix calculation of max register number
Christian König
2012-08-01
1
-1
/
+1
*
radeon/llvm: Add pseudo-support for 64-bit immediate types on SI
Tom Stellard
2012-07-31
2
-0
/
+23
*
radeon/llvm: Fix incorrect return value in SelectADDRReg()
Tom Stellard
2012-07-31
1
-1
/
+1
*
radeon/llvm: Move SMRD IMM pattern before SMRD SGPR pattern
Tom Stellard
2012-07-31
1
-7
/
+6
*
radeon/llvm: Cleanup AMDIL.h
Tom Stellard
2012-07-30
4
-91
/
+26
*
radeon/llvm: Rename all AMDIL* classes to AMDGPU*
Tom Stellard
2012-07-30
30
-496
/
+496
*
radeon/llvm: Merge AMDILSubtarget into AMDGPUSubtarget
Tom Stellard
2012-07-30
25
-324
/
+156
*
radeon/llvm: Merge AMDILTargetLowering class into AMDGPUTargetLowering
Tom Stellard
2012-07-30
11
-241
/
+144
*
radeon/llvm: Remove IL_cmp DAG node
Tom Stellard
2012-07-30
4
-502
/
+2
*
radeon/llvm: Cleanup and reorganize AMDIL .td files
Tom Stellard
2012-07-30
13
-2303
/
+335
*
radeon/llvm: Remove lowering code for unsupported features
Tom Stellard
2012-07-30
8
-805
/
+50
*
radeon/llvm: Remove AMDILVersion.td
Tom Stellard
2012-07-30
2
-59
/
+0
*
radeon/llvm: Remove AMDILAlgorithms.tpp
Tom Stellard
2012-07-30
2
-94
/
+19
*
radeon/llvm: Merge AMDILInstrInfo.cpp into AMDGPUInstrInfo.cpp
Tom Stellard
2012-07-30
12
-693
/
+512
*
radeon/llvm: Merge AMDILRegisterInfo into AMDGPURegisterInfo
Tom Stellard
2012-07-30
12
-283
/
+69
*
radeon/llvm: Change the tablegen target from AMDIL to AMDGPU
Tom Stellard
2012-07-30
14
-107
/
+119
*
radeon/llvm: Add instruction defs for branches on SI
Tom Stellard
2012-07-27
3
-17
/
+126
*
radeon/llvm: Fix VOPC and V_CNDMASK encoding
Tom Stellard
2012-07-27
4
-10
/
+13
*
radeon/llvm: Assert if we try to copy SCC reg
Tom Stellard
2012-07-27
1
-0
/
+6
*
radeon/llvm: Add SI DAG optimizations for setcc, select_cc
Tom Stellard
2012-07-27
2
-0
/
+54
*
radeon/llvm: Add support for encoding SI branch instructions
Tom Stellard
2012-07-27
1
-15
/
+35
*
radeon/llvm: Add special nodes for SALU operations on VCC
Tom Stellard
2012-07-27
6
-1
/
+89
*
radeon/llvm: Add i1 registers for SI.
Tom Stellard
2012-07-27
1
-0
/
+2
*
radeon/llvm: Fix CCReg definitions on SI
Tom Stellard
2012-07-27
2
-3
/
+10
*
radeon/llvm: Add bitconvert patterns for SI
Tom Stellard
2012-07-27
1
-0
/
+6
*
radeon/llvm: Add custom lowering for SELECT_CC nodes on SI
Tom Stellard
2012-07-27
2
-0
/
+20
*
radeon/llvm: Move conditional pattern leafs to common tablegen file
Tom Stellard
2012-07-27
2
-41
/
+41
*
radeon/llvm: Implement getSetCCResultType for SI
Tom Stellard
2012-07-27
2
-0
/
+6
*
radeon/llvm: Custom lower BR_CC for SI
Tom Stellard
2012-07-27
2
-0
/
+41
*
radeon/llvm: Move lowering of BR_CC node to R600ISelLowering
Tom Stellard
2012-07-27
4
-31
/
+31
*
radeon/llvm: Move lowering of SETCC node to R600ISelLowering
Tom Stellard
2012-07-27
4
-38
/
+29
*
radeon/llvm: Use correct node type when lowering SETCC
Tom Stellard
2012-07-27
1
-0
/
+1
*
radeon/llvm: Move LowerSELECT_CC into R600ISelLowering
Tom Stellard
2012-07-27
4
-111
/
+112
*
radeon/llvm: Fix a bug with IF LOGICALNZ with int operand
Vincent Lejeune
2012-07-23
2
-3
/
+5
*
radeon/llvm: Fix CR/LF in AMDILSIDevice.h
Andreas Boll
2012-07-13
1
-1
/
+1
*
radeon/llvm: Clean up AMDILIntrinsicInfo.cpp
Tom Stellard
2012-07-13
2
-84
/
+5
*
radeon/llvm: Coding style fixes
Tom Stellard
2012-07-13
2
-409
/
+325
*
radeon/llvm: Don't use lp_build_swizzle_aos() for swizzles
Tom Stellard
2012-07-12
1
-8
/
+13
*
radeon/llvm: Use multiclasses for floating point loads
Tom Stellard
2012-07-11
7
-50
/
+46
*
radeon/llvm: Don't set the IMM bit in SMRD instruction definitions.
Tom Stellard
2012-07-11
1
-7
/
+2
*
radeon/llvm: Rename namespace from AMDIL to AMDGPU
Tom Stellard
2012-07-09
25
-360
/
+361
*
radeon/llvm: Enable vec4 loads on R600
Tom Stellard
2012-06-29
3
-0
/
+20
*
radeon/llvm: Enable floating point stores on R600
Tom Stellard
2012-06-29
1
-0
/
+6
*
radeon/llvm: Handle floating point loads on R600
Tom Stellard
2012-06-29
2
-0
/
+31
*
radeon/llvm: Expand UDIV and UREM nodes
Tom Stellard
2012-06-29
1
-4
/
+3
*
radeon/llvm: Emit raw ISA for vertex fetch instructions
Tom Stellard
2012-06-29
2
-61
/
+99
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