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* radeon/llvm: Add support for i8 reads on R600Tom Stellard2012-09-213-0/+25
* radeon/llvm: Expand vector fadd and fmul on R600Tom Stellard2012-09-211-0/+3
* radeon/llvm: Add optimization for FP_ROUNDTom Stellard2012-09-212-0/+27
* radeon/llvm: Replace AMDGPU pow intrinsic with the llvm versionTom Stellard2012-09-214-7/+26
* radeon/llvm: Emit ISA for ALU instructions in the R600 code emitterMichal Sciubidlo2012-09-195-139/+238
* radeon/llvm: Only support 512 constant registers on R600Tom Stellard2012-09-191-1/+1
* radeon/llvm: Add a fdiv pattern.Vincent Lejeune2012-09-181-3/+10
* radeon/llvm: reserve also corresponding 128bits regVincent Lejeune2012-09-181-0/+1
* radeon/llvm: Inital flow control support for SITom Stellard2012-09-177-2/+168
* radeon/llvm: Fix unused variable warningTom Stellard2012-09-171-1/+0
* radeon/llvm: Move kernel arg lowering into R600TargetLowering classTom Stellard2012-09-176-470/+35
* radeon/llvm: Match integer add/sub for SI.Michel Dänzer2012-09-171-2/+8
* radeon/llvm: Complete integer comparison patterns for SI.Michel Dänzer2012-09-171-4/+12
* radeon/llvm: Match AMDGPUfract on SI.Michel Dänzer2012-09-171-1/+3
* radeon/llvm: Match int_AMDGPU_floor for SI.Michel Dänzer2012-09-171-1/+3
* radeon/llvm: Match vector logical operations on SI.Michel Dänzer2012-09-171-3/+9
* radeon/llvm: Support frint on SIChristian König2012-09-141-1/+3
* radeon/llvm: Fix lowering of vbuildTom Stellard2012-09-137-93/+19
* radeon/llvm: Support fmul on SITom Stellard2012-09-131-1/+4
* radeon/llvm: Fix operand order of V_CNDMASK in custom inserterTom Stellard2012-09-111-1/+1
* radeon/llvm: Assert if we try to encode an unknown registerTom Stellard2012-09-111-1/+1
* radeon/llvm: Add register encoding for VCCTom Stellard2012-09-111-0/+1
* radeon/llvm: Ignore special registers when calculating reg countTom Stellard2012-09-111-0/+2
* radeonsi: Handle position input parameter for pixel shaders v2Tom Stellard2012-09-112-0/+22
* radeon/llvm: Coding style fixesTom Stellard2012-09-114-31/+31
* radeonsi: Move interpolation mode check into the compilerTom Stellard2012-09-111-1/+12
* radeon/llvm: Add SHADER_TYPE instructionTom Stellard2012-09-118-1/+32
* radeon/llvm: Match fexp2 for SI.Michel Dänzer2012-09-071-1/+3
* radeon/llvm: Add intrinsic for enabling whole quad mode in SI pixel shaders.Michel Dänzer2012-09-064-0/+23
* radeon/llvm: SI shader vector instructions implicitly use the EXEC register.Michel Dänzer2012-09-061-0/+4
* radeon/llvm: Extend SI EXEC register support.Michel Dänzer2012-09-062-2/+7
* radeon/llvm: Remove R600InstrInfo.td from TD_FILESTom Stellard2012-09-061-1/+0
* radeon/llvm: Cleanup makefileTom Stellard2012-09-062-13/+37
* radeon/llvm: Fix operand ordering for V_CNDMASK_B32Tom Stellard2012-09-051-3/+3
* radeon/llvm: Use correct float->int conversion opcode on SI.Tom Stellard2012-09-051-2/+4
* radeon/llvm: Fix lowering of SI_V_CNDLTTom Stellard2012-09-041-3/+3
* radeon/llvm: Fix encoding of V_CNDMASK_B32Tom Stellard2012-09-042-4/+4
* radeon/llvm: do not convert f32 operand of select_cc nodeVincent Lejeune2012-09-041-20/+20
* radeon/llvm: custom lowering for FP_TO_UINT when dst is i1 (bool)Vincent Lejeune2012-09-042-2/+26
* radeon/llvm: support setcc on f32Vincent Lejeune2012-09-041-9/+27
* radon/llvm: br_cc f32 now lowered without castVincent Lejeune2012-09-041-9/+24
* radeon/llvm: swap wrong OPCODE_IS_*_ZERO_* opcode and useVincent Lejeune2012-09-042-4/+4
* radeon/llvm: fix SelectADDR8BitOffsetChristian König2012-09-041-1/+1
* radeon/llvm: Rework how immediate operands are handled with SITom Stellard2012-08-3110-44/+150
* radeon/llvm: Fix typo in assertTom Stellard2012-08-311-1/+1
* radeon/llvm: Fix isEG tablegen predicateTom Stellard2012-08-311-3/+5
* radeon/llvm: Add support for RCP instruction on SITom Stellard2012-08-311-1/+3
* radeon/llvm: Support AMDGPUfmin DAG node on SITom Stellard2012-08-311-1/+3
* radeon/llvm: Fix encoding of FP immediates on SITom Stellard2012-08-291-1/+6
* radeon/llvm: Create a register class for the M0 registerTom Stellard2012-08-295-16/+24
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