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gallium
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drivers
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radeon
Commit message (
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Author
Age
Files
Lines
*
r600g/llvm: Set Inputs/Outputs count to 32 (api reported value)
Vincent Lejeune
2013-02-18
1
-2
/
+2
*
r600g/llvm: Fix alpha_to_one piglit tests
Vincent Lejeune
2013-02-18
1
-0
/
+1
*
r600g/llvm: Add support for UBO
Vincent Lejeune
2013-02-18
1
-0
/
+17
*
radeonsi: Adapt to sample intrinsics changes.
Michel Dänzer
2013-02-04
2
-27
/
+25
*
r600g: improve inputs/interpolation handling with llvm backend
Vadim Girlin
2013-01-28
1
-2
/
+1
*
radeon/llvm: Handle LP_CHAN_ALL in emit_fetch_immediate().
Michel Dänzer
2013-01-22
1
-1
/
+11
*
r600g/llvm: tgsi to llvm emits store.swizzle intrinsic for vs/fs output
Vincent Lejeune
2013-01-18
1
-0
/
+1
*
r600g/llvm: tgsi to llvm emits stream output intrinsics.
Vincent Lejeune
2013-01-18
1
-0
/
+1
*
r600g/llvm:translate ARL opcode to a simple cast
Vincent Lejeune
2013-01-18
1
-2
/
+12
*
r600g/llvm: rework handling of the constants
Vadim Girlin
2013-01-18
1
-0
/
+4
*
drivers/radeon: Don't link against libgallium.la
Tom Stellard
2013-01-11
1
-2
/
+1
*
radeon/llvm: Convert to Automake
Tom Stellard
2013-01-10
3
-17
/
+33
*
radeon/llvm: Remove backend code from Mesa
Tom Stellard
2013-01-04
99
-19168
/
+0
*
Support LLVM >= 3.2 on radeonsi and opencl.
Johannes Obermayr
2013-01-04
1
-0
/
+7
*
radeon/llvm: improve cube map handling
Vadim Girlin
2012-12-18
2
-20
/
+69
*
radeon/llvm: fix TXQ_LZ handling for cube maps
Vadim Girlin
2012-12-18
1
-2
/
+4
*
radeon/llvm: Export prepare_cube_coords helper to driver.
Michel Dänzer
2012-12-06
2
-8
/
+13
*
r600g: use default action for min/max opcode in tgsi to llvm
Vincent Lejeune
2012-12-05
1
-4
/
+0
*
r600g: use default action for fdiv/rcp opcode
Vincent Lejeune
2012-12-05
1
-6
/
+1
*
r600g: Use default mul/mad function for tgsi-to-llvm
Vincent Lejeune
2012-12-05
1
-8
/
+4
*
r600g: make tgsi-to-llvm generates store.pixel* intrinsic for fs
Vincent Lejeune
2012-11-02
1
-0
/
+3
*
radeon/llvm: Add intrinsic for reading SI FRONT_FACE VGPR in the pixel shader.
Michel Dänzer
2012-10-26
2
-0
/
+6
*
radeon/llvm: Sort tgsi opcode action initialization
Tom Stellard
2012-10-19
1
-59
/
+50
*
radeon/llvm: Fix lowering TGSI_OPCODE_SSG
Tom Stellard
2012-10-19
1
-1
/
+1
*
radeon/llvm: Fix build with LLVM 3.2
Tom Stellard
2012-10-11
1
-3
/
+10
*
radeon/llvm: use ceil intrinsic instead of llvm.AMDIL.round.posinf
Vincent Lejeune
2012-10-10
3
-6
/
+2
*
radeon/llvm: use floor intrinsic instead of llvm.AMDIL.floor
Vincent Lejeune
2012-10-10
5
-5
/
+5
*
radeon/llvm: use llvm fabs intrinsic
Vincent Lejeune
2012-10-10
3
-6
/
+4
*
radeon/llvm: use llvm intrinsic for flog2
Vincent Lejeune
2012-10-10
4
-5
/
+4
*
radeon/llvm: add support for cos/sin intrinsic
Vincent Lejeune
2012-10-10
3
-12
/
+15
*
radeon/llvm: add a pattern for fsqrt
Vincent Lejeune
2012-10-10
1
-0
/
+3
*
radeon/llvm: Disable SI flow control again for now.
Michel Dänzer
2012-10-02
1
-1
/
+2
*
radeon/llvm: Only initialize the AMDGPU target
Tom Stellard
2012-10-01
1
-7
/
+1
*
radeon: Fix build with LLVM 3.1
Tom Stellard
2012-10-01
1
-0
/
+1
*
radeon: Support LLVM 3.2
Tom Stellard
2012-10-01
3
-3
/
+11
*
r600g: add some members to radeon_llvm_context
Vincent Lejeune
2012-09-28
1
-0
/
+6
*
radeon/llvm: improve select_cc lowering to generate CND* more often
Vincent Lejeune
2012-09-27
3
-41
/
+88
*
radeon/llvm: Fix instruction encoding for r600 family GPUs
Tom Stellard
2012-09-24
3
-15
/
+14
*
radeon/llvm: support for interpolation intrinsics
Vincent Lejeune
2012-09-22
10
-2
/
+318
*
radeon/llvm: Handle loads from the constants address space.
Tom Stellard
2012-09-21
2
-0
/
+10
*
radeon/llvm: Add support for v4f32 stores on R600
Tom Stellard
2012-09-21
3
-9
/
+27
*
radeon/llvm: Add support for i8 reads on R600
Tom Stellard
2012-09-21
3
-0
/
+25
*
radeon/llvm: Expand vector fadd and fmul on R600
Tom Stellard
2012-09-21
1
-0
/
+3
*
radeon/llvm: Add optimization for FP_ROUND
Tom Stellard
2012-09-21
2
-0
/
+27
*
radeon/llvm: Replace AMDGPU pow intrinsic with the llvm version
Tom Stellard
2012-09-21
4
-7
/
+26
*
radeon/llvm: Emit ISA for ALU instructions in the R600 code emitter
Michal Sciubidlo
2012-09-19
5
-139
/
+238
*
radeon/llvm: Only support 512 constant registers on R600
Tom Stellard
2012-09-19
1
-1
/
+1
*
radeon/llvm: Add a fdiv pattern.
Vincent Lejeune
2012-09-18
1
-3
/
+10
*
radeon/llvm: reserve also corresponding 128bits reg
Vincent Lejeune
2012-09-18
1
-0
/
+1
*
radeon/llvm: Inital flow control support for SI
Tom Stellard
2012-09-17
7
-2
/
+168
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