| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | radeon/llvm: fix opcode for RECIP_UINT_r600 | Vadim Girlin | 2012-05-25 | 1 | -1/+1 |
| | | | | | | | | | Fixes https://bugs.freedesktop.org/show_bug.cgi?id=50312 Signed-off-by: Vadim Girlin <[email protected]> Tested-by: Kai Wasserbäch <[email protected]> Reviewed-by: Tom Stellard <[email protected]> | ||||
| * | radeon/llvm/loader: convert hardcoded gpu name to option | Vadim Girlin | 2012-05-25 | 1 | -2/+3 |
| | | | | | | Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]> | ||||
| * | radeon/llvm: Lower UDIV using the Selection DAG | Tom Stellard | 2012-05-24 | 8 | -212/+126 |
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| * | radeon/llvm: Remove auto-generated AMDIL->ISA conversion code | Tom Stellard | 2012-05-24 | 14 | -280/+28 |
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| * | radeon/llvm: Remove AMDIL instructions MULHI, SMUL | Tom Stellard | 2012-05-24 | 3 | -10/+5 |
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| * | radeon/llvm: Remove AMDIL bitshift instructions (SHL, SHR, USHR) | Tom Stellard | 2012-05-24 | 8 | -693/+6 |
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| * | radeon/llvm: Remove AMDIL FTOI and ITOF instructions | Tom Stellard | 2012-05-24 | 7 | -316/+7 |
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| * | radeon/llvm: Remove AMDIL EXP* instructions | Tom Stellard | 2012-05-24 | 5 | -15/+7 |
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| * | radeon/llvm: Remove AMDIL ADD instructions | Tom Stellard | 2012-05-24 | 6 | -179/+4 |
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| * | radeon/llvm: Remove AMDIL binary instrutions (OR, AND, XOR, NOT) | Tom Stellard | 2012-05-24 | 8 | -422/+8 |
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| * | radeon/llvm: Remove AMDILMachinePeephole pass | Tom Stellard | 2012-05-24 | 4 | -177/+0 |
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| * | radeon/llvm: Remove AMDIL CMP instructions and associated lowering code | Tom Stellard | 2012-05-24 | 3 | -661/+22 |
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| * | radeon/llvm: Remove AMDIL ROUND_NEAREST instruction | Tom Stellard | 2012-05-24 | 4 | -6/+6 |
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| * | radeon/llvm: Remove AMDIL ROUND_POSINF instruction | Tom Stellard | 2012-05-24 | 4 | -6/+10 |
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| * | radeon/llvm: Add custom SDNode for FRACT | Tom Stellard | 2012-05-24 | 6 | -6/+10 |
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| * | radeon/llvm: Use -1 as true value for SET* integer instructions | Tom Stellard | 2012-05-24 | 3 | -32/+28 |
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| * | radeon/llvm: Handle SETGE_INT, SETGE_UINT, and SETGT_UINT opcodes | Tom Stellard | 2012-05-24 | 1 | -0/+6 |
| | | | | | | Support for these was inadvertently dropped in commit cee23ab246f22210b3063cdc47bdb45b3d943526 | ||||
| * | radeon/llvm: Avoid error with SI in EmitInstrWithCustomInserter() | Tom Stellard | 2012-05-24 | 1 | -0/+1 |
| | | | | | | | We need to return immediately after inserting instructions that require S_WAITCNT so that the parent class' custom inserter won't try to insert them again. | ||||
| * | radeon/llvm: Handle selectcc DAG node | Tom Stellard | 2012-05-20 | 7 | -54/+350 |
| | | | | | | R600 can now select instructions from the selectcc DAG node, which is typically lowered to one of the SET* instructions. | ||||
| * | radeon/llvm: Fix segfault while lowering lrp intrinsic | Tom Stellard | 2012-05-17 | 1 | -2/+3 |
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| * | radeon/llvm: Add DAG nodes for MIN instructions | Tom Stellard | 2012-05-17 | 6 | -14/+38 |
| | | | | | Also, remove the AMDIL MIN* instruction defs. | ||||
| * | radeon/llvm: Lower lrp intrinsic during ISel | Tom Stellard | 2012-05-17 | 3 | -7/+19 |
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| * | radeon/llvm: Remove AMDIL MAD instruction defs | Tom Stellard | 2012-05-17 | 6 | -7/+14 |
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| * | radeon/llvm: Remove AMDIL MUL_IEEE* instructions | Tom Stellard | 2012-05-17 | 3 | -7/+3 |
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| * | radeon/llvm: Expand fsub during ISel | Tom Stellard | 2012-05-17 | 2 | -11/+2 |
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| * | radeon/llvm: Remove AMDIL floating-point ADD instruction defs | Tom Stellard | 2012-05-17 | 5 | -8/+9 |
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| * | radeon/llvm: Remove AMDIL CMOVLOG* instruction defs | Tom Stellard | 2012-05-17 | 4 | -26/+6 |
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| * | radeon/llvm: Move lowering of ABS_i32 to ISel | Tom Stellard | 2012-05-17 | 4 | -17/+16 |
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| * | radeon/llvm: Remove sub patterns from AMDILInstrPatterns.td | Tom Stellard | 2012-05-17 | 2 | -21/+1 |
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| * | radeon/llvm: Add custom SDNodes for MAX | Tom Stellard | 2012-05-17 | 10 | -10/+108 |
| | | | | | | We now lower the various intrinsics for max to SDNodes and then use tablegen patterns to lower the SDNodes to instructions. | ||||
| * | radeon/llvm: add support for texture offsets, fix TEX_LD | Vadim Girlin | 2012-05-15 | 4 | -10/+51 |
| | | | | | | Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]> | ||||
| * | radeon/llvm: add SET_GRADIENTS*, fix SAMPLE_G | Vadim Girlin | 2012-05-15 | 5 | -4/+96 |
| | | | | | | Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]> | ||||
| * | radeon/llvm: increase const regs count | Vadim Girlin | 2012-05-15 | 1 | -1/+1 |
| | | | | | | Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]> | ||||
| * | radeon/llvm: use IntrNoMem property for intrinsics where possible | Vadim Girlin | 2012-05-15 | 6 | -95/+158 |
| | | | | | | Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]> | ||||
| * | radeon/llvm: use correct intrinsic for CEIL | Vadim Girlin | 2012-05-15 | 2 | -3/+3 |
| | | | | | | | | Should be round_posinf instead of round_neginf. Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]> | ||||
| * | radeon/llvm: improve ABS_i32 lowering | Vadim Girlin | 2012-05-15 | 1 | -13/+5 |
| | | | | | | | | | | We can save one instruction by lowering it to: SUB_INT tmp, 0, src MAX_INT dst, src, tmp Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]> | ||||
| * | radeon/llvm: fix BUILD_VECTOR lowering for replicated value | Vadim Girlin | 2012-05-15 | 1 | -0/+2 |
| | | | | | | | | We expect that all elements will be assigned even if they are equal Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]> | ||||
| * | radeon/llvm: add names for AMDGPU* passes | Vadim Girlin | 2012-05-15 | 2 | -0/+5 |
| | | | | | | Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]> | ||||
| * | radeon/llvm: add generated files to .gitignore | Vadim Girlin | 2012-05-15 | 1 | -0/+18 |
| | | | | | | Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]> | ||||
| * | radeonsi: Flesh out shader interpolation related code. | Michel Dänzer | 2012-05-14 | 2 | -0/+21 |
| | | | | | Handle perspective interpolation and ceontroid vs. center. | ||||
| * | radeon/llvm: Coding style fixes for R600CodeEmitter.cpp | Tom Stellard | 2012-05-14 | 1 | -148/+90 |
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| * | radeon/llvm: Lower bitcast instructions to copies | Tom Stellard | 2012-05-14 | 1 | -0/+10 |
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| * | radeon/llvm: More comments and cleanups | Tom Stellard | 2012-05-11 | 22 | -163/+190 |
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| * | radeon/llvm: Fix Evergreen/Cayman tablegen predicates | Tom Stellard | 2012-05-11 | 1 | -1/+3 |
| | | | | | Some Evergreen/Cayman instructions were being enabled for SI. | ||||
| * | radeon/llvm: Remove AMDILMCCodeEmitter.cpp | Tom Stellard | 2012-05-10 | 2 | -158/+0 |
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| * | radeon/llvm: Remove SILowerShaderInstructions.cpp | Tom Stellard | 2012-05-10 | 4 | -81/+0 |
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| * | radeonsi/llvm: Move lowering of RETURN to ConvertToISA pass | Tom Stellard | 2012-05-10 | 2 | -11/+2 |
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| * | radeon/llvm: Add some comments | Tom Stellard | 2012-05-10 | 64 | -422/+393 |
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| * | radeon/llvm: Move util functions into AMDGPU namespace | Tom Stellard | 2012-05-10 | 3 | -39/+37 |
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| * | radeon/llvm: Auto-encode RAT_WRITE_CACHELESS_eg | Tom Stellard | 2012-05-10 | 2 | -17/+0 |
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