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* radeon/llvm: Add intrinsic for enabling whole quad mode in SI pixel shaders.Michel Dänzer2012-09-064-0/+23
| | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: SI shader vector instructions implicitly use the EXEC register.Michel Dänzer2012-09-061-0/+4
| | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: Extend SI EXEC register support.Michel Dänzer2012-09-062-2/+7
| | | | | | | Add 32 bit lo and hi variants, and binary encodings. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: Remove R600InstrInfo.td from TD_FILESTom Stellard2012-09-061-1/+0
| | | | | Fixes build bug introduced by cebbdd4ac23725963207bf6f8fc7101150e6065f
* radeon/llvm: Cleanup makefileTom Stellard2012-09-062-13/+37
| | | | | Hopefully, this will fix all the parallel make problems people have been having.
* radeon/llvm: Fix operand ordering for V_CNDMASK_B32Tom Stellard2012-09-051-3/+3
| | | | This fixes several hundred piglit tests.
* radeon/llvm: Use correct float->int conversion opcode on SI.Tom Stellard2012-09-051-2/+4
| | | | | V_CVT_I32_F32 converts floats to signed integers, but we were using V_CVT_F32_I32 which convertes signed integers to float.
* radeon/llvm: Fix lowering of SI_V_CNDLTTom Stellard2012-09-041-3/+3
| | | | | SREG_LIT_0 is a scalar register, so it can only be used in the first argument of vector instructoins.
* radeon/llvm: Fix encoding of V_CNDMASK_B32Tom Stellard2012-09-042-4/+4
| | | | | | | The CodeEmitter was not setting the VGPR bit for src0, because the instruction definition had the VCC register in the src0 slot, instead of the actual src0 register. This has been fixed by moving the VCC register to the end of the operand list.
* radeon/llvm: do not convert f32 operand of select_cc nodeVincent Lejeune2012-09-041-20/+20
| | | | | | v2:-use camel coding style Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: custom lowering for FP_TO_UINT when dst is i1 (bool)Vincent Lejeune2012-09-042-2/+26
| | | | | | v2:-wrap line at 80 characters Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: support setcc on f32Vincent Lejeune2012-09-041-9/+27
| | | | Reviewed-by: Tom Stellard <[email protected]>
* radon/llvm: br_cc f32 now lowered without castVincent Lejeune2012-09-041-9/+24
| | | | Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: swap wrong OPCODE_IS_*_ZERO_* opcode and useVincent Lejeune2012-09-042-4/+4
| | | | Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: fix SelectADDR8BitOffsetChristian König2012-09-041-1/+1
| | | | | | | The offset is unsigned, not signed. Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeon/llvm: Rework how immediate operands are handled with SITom Stellard2012-08-3110-44/+150
| | | | | | | Immediate operands were previously handled in the CodeEmitter, but that code was buggy and very confusing. This commit adds a pass that simplifies the handling of immediate operands by spliting the loading of the immediate into a sperate insruction that is bundled with the original.
* radeon/llvm: Fix typo in assertTom Stellard2012-08-311-1/+1
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* radeon/llvm: Fix isEG tablegen predicateTom Stellard2012-08-311-3/+5
| | | | | This predicate incorrectly included SI GPUs, so some Evergreen instructions were being emmitted on SI.
* radeon/llvm: Add support for RCP instruction on SITom Stellard2012-08-311-1/+3
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* radeon/llvm: Support AMDGPUfmin DAG node on SITom Stellard2012-08-311-1/+3
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* radeon/llvm: Fix encoding of FP immediates on SITom Stellard2012-08-291-1/+6
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* radeon/llvm: Create a register class for the M0 registerTom Stellard2012-08-295-16/+24
| | | | | | | | | | | The Common Subexpression Elimination pass will not operate on instructions with physical register defs, so we end up with several redundant copies to M0 when using interpolation. Adding a register class that only contains the M0 register allows use to use a virtual register to represent M0, and makes it possible for the Common Subexpression Elimination pass to remove the extra copies.
* radeon/llvm: Set the neverHasSideEffects bit on more instructionsTom Stellard2012-08-291-0/+2
| | | | | This flag makes these instructions candidates for the dead code elimination and common subexpression elimination.
* radeon/llvm: Declare the interpolation intrinsics as ReadOnlyTom Stellard2012-08-292-1/+2
| | | | | This signals to the Dead Code Elimination pass that it is safe to remove these instructions when they are dead.
* radeon/llvm: Mark M0 as a def when lowering interpolation instructionsTom Stellard2012-08-291-4/+2
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* radeon/llvm: Handle TGSI KIL opcode for SI.Michel Dänzer2012-08-283-0/+44
| | | | | | | Fixes piglit fp-kil and glBitmap() with radeonsi. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: Basic support for SI EXEC register.Michel Dänzer2012-08-283-2/+23
| | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeonsi: Use FP16 shader export format when necessary / possible.Michel Dänzer2012-08-272-1/+4
| | | | | | | | | Fixes piglit fbo-blending-formats. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeon/llvm: Cleanup R600Instructions.tdTom Stellard2012-08-242-93/+28
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* radeon/llvm: Set End of Program bit on RAT instructionsTom Stellard2012-08-233-10/+14
| | | | This code was accidently dropped during the MCCodeEmitter conversion.
* radeon/llvm: Use correct instruction for moving immediatesTom Stellard2012-08-231-1/+2
| | | | | This should fix an assertion failure that was happening in some compute shaders.
* radeon/llvm: Fix some coding style issuesTom Stellard2012-08-2314-82/+135
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* radeon/llvm: Pull changes from external version of the backendTom Stellard2012-08-2321-76/+38
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* radeon/llvm: Simplify the convert to ISA passTom Stellard2012-08-233-20/+7
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* radeon/llvm: Make sure to use the Text section in the AsmPrinterTom Stellard2012-08-231-0/+2
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* radeon/llvm: Use the MCCodeEmitter for R600Tom Stellard2012-08-2316-738/+779
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* radeon/llvm: Use the MCCodeEmitter for SITom Stellard2012-08-2315-431/+591
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* radeon/llvm: Set 64BitPtr feature bit for SITom Stellard2012-08-231-1/+1
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* radeon/llvm: Lower RETFLAG DAG Node to S_ENDPGM on SITom Stellard2012-08-233-8/+12
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* radeon/llvm: Add AsmPrinterTom Stellard2012-08-238-0/+193
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* radeon/llvm: Mark JUMP as a pseudo instructionTom Stellard2012-08-231-1/+1
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* radeon/llvm: Remove the last uses of MachineOperand flagsTom Stellard2012-08-232-8/+27
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* radeon/llvm: Add flag operand to some instructionsTom Stellard2012-08-237-33/+97
| | | | | | | This new operand replaces the MachineOperand flags in LLVM, which will be deprecated soon. Eventually all instructions should have a flag operand, but for now this operand has only been added to instructions that need it.
* radeon/llvm: Encapsulate setting of MachineOperand flagsTom Stellard2012-08-234-50/+71
| | | | | MachineOperand flags will be removed soon, so it is convienent to have only one function that modifies them.
* radeon/llvm: ExpandSpecialInstrs - Add support for cube instructionsTom Stellard2012-08-214-63/+100
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* radeon/llvm: ExpandSpecialInstrs - Add support for vector instructionsTom Stellard2012-08-212-15/+30
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* radeon/llvm: Add R600ExpandSpecialInstrs passTom Stellard2012-08-216-14/+112
| | | | | This pass expends reduction instructions into a MachineInstrBundle that contains 4 instruction, one for each instruction slot.
* radeon/llvm: Add helper function for getting sub reg indicesTom Stellard2012-08-213-6/+19
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* radeon-llvm: Start multithreaded before using llvm.Mathias Fröhlich2012-08-201-0/+15
| | | | | | | | | | | | | | | | | | | This is required to make some of llvm's api calls thread save. In particular the PassRegistry, which is implicitly accessed while compiling shader programs. The PassRegistry uses a mutex that is only active if the llvm_is_multithreaded() returns true. Calling llvm_start_multithreading() makes this happen and by calling this function we try to make sure that we can savely compile shaders in paralell. Since there is also a call llvm_stop_multithreading() in the llvm api, we cannot guarantee that this does not get switched off while we are relying on this being set, but for the easier use cases this fixes a race with the radeon llvm compiler we have as of today. Signed-off-by: Mathias Froehlich <[email protected]> Signed-off-by: Tom Stellard <[email protected]>
* radeon/llvm: Lower implicit parameters before ISelTom Stellard2012-08-163-69/+42
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