mesa.git - Unnamed repository; edit this file 'description' to name the repository.

	Commit message (Expand)	Author	Age	Files	Lines
*	radeon/llvm: Add intrinsic for enabling whole quad mode in SI pixel shaders.	Michel Dänzer	2012-09-06	4	-0/+23
*	radeon/llvm: SI shader vector instructions implicitly use the EXEC register.	Michel Dänzer	2012-09-06	1	-0/+4
*	radeon/llvm: Extend SI EXEC register support.	Michel Dänzer	2012-09-06	2	-2/+7
*	radeon/llvm: Remove R600InstrInfo.td from TD_FILES	Tom Stellard	2012-09-06	1	-1/+0
*	radeon/llvm: Cleanup makefile	Tom Stellard	2012-09-06	2	-13/+37
*	radeon/llvm: Fix operand ordering for V_CNDMASK_B32	Tom Stellard	2012-09-05	1	-3/+3
*	radeon/llvm: Use correct float->int conversion opcode on SI.	Tom Stellard	2012-09-05	1	-2/+4
*	radeon/llvm: Fix lowering of SI_V_CNDLT	Tom Stellard	2012-09-04	1	-3/+3
*	radeon/llvm: Fix encoding of V_CNDMASK_B32	Tom Stellard	2012-09-04	2	-4/+4
*	radeon/llvm: do not convert f32 operand of select_cc node	Vincent Lejeune	2012-09-04	1	-20/+20
*	radeon/llvm: custom lowering for FP_TO_UINT when dst is i1 (bool)	Vincent Lejeune	2012-09-04	2	-2/+26
*	radeon/llvm: support setcc on f32	Vincent Lejeune	2012-09-04	1	-9/+27
*	radon/llvm: br_cc f32 now lowered without cast	Vincent Lejeune	2012-09-04	1	-9/+24
*	radeon/llvm: swap wrong OPCODE_IS__ZERO_ opcode and use	Vincent Lejeune	2012-09-04	2	-4/+4
*	radeon/llvm: fix SelectADDR8BitOffset	Christian König	2012-09-04	1	-1/+1
*	radeon/llvm: Rework how immediate operands are handled with SI	Tom Stellard	2012-08-31	10	-44/+150
*	radeon/llvm: Fix typo in assert	Tom Stellard	2012-08-31	1	-1/+1
*	radeon/llvm: Fix isEG tablegen predicate	Tom Stellard	2012-08-31	1	-3/+5
*	radeon/llvm: Add support for RCP instruction on SI	Tom Stellard	2012-08-31	1	-1/+3
*	radeon/llvm: Support AMDGPUfmin DAG node on SI	Tom Stellard	2012-08-31	1	-1/+3
*	radeon/llvm: Fix encoding of FP immediates on SI	Tom Stellard	2012-08-29	1	-1/+6
*	radeon/llvm: Create a register class for the M0 register	Tom Stellard	2012-08-29	5	-16/+24
*	radeon/llvm: Set the neverHasSideEffects bit on more instructions	Tom Stellard	2012-08-29	1	-0/+2
*	radeon/llvm: Declare the interpolation intrinsics as ReadOnly	Tom Stellard	2012-08-29	2	-1/+2
*	radeon/llvm: Mark M0 as a def when lowering interpolation instructions	Tom Stellard	2012-08-29	1	-4/+2
*	radeon/llvm: Handle TGSI KIL opcode for SI.	Michel Dänzer	2012-08-28	3	-0/+44
*	radeon/llvm: Basic support for SI EXEC register.	Michel Dänzer	2012-08-28	3	-2/+23
*	radeonsi: Use FP16 shader export format when necessary / possible.	Michel Dänzer	2012-08-27	2	-1/+4
*	radeon/llvm: Cleanup R600Instructions.td	Tom Stellard	2012-08-24	2	-93/+28
*	radeon/llvm: Set End of Program bit on RAT instructions	Tom Stellard	2012-08-23	3	-10/+14
*	radeon/llvm: Use correct instruction for moving immediates	Tom Stellard	2012-08-23	1	-1/+2
*	radeon/llvm: Fix some coding style issues	Tom Stellard	2012-08-23	14	-82/+135
*	radeon/llvm: Pull changes from external version of the backend	Tom Stellard	2012-08-23	21	-76/+38
*	radeon/llvm: Simplify the convert to ISA pass	Tom Stellard	2012-08-23	3	-20/+7
*	radeon/llvm: Make sure to use the Text section in the AsmPrinter	Tom Stellard	2012-08-23	1	-0/+2
*	radeon/llvm: Use the MCCodeEmitter for R600	Tom Stellard	2012-08-23	16	-738/+779
*	radeon/llvm: Use the MCCodeEmitter for SI	Tom Stellard	2012-08-23	15	-431/+591
*	radeon/llvm: Set 64BitPtr feature bit for SI	Tom Stellard	2012-08-23	1	-1/+1
*	radeon/llvm: Lower RETFLAG DAG Node to S_ENDPGM on SI	Tom Stellard	2012-08-23	3	-8/+12
*	radeon/llvm: Add AsmPrinter	Tom Stellard	2012-08-23	8	-0/+193
*	radeon/llvm: Mark JUMP as a pseudo instruction	Tom Stellard	2012-08-23	1	-1/+1
*	radeon/llvm: Remove the last uses of MachineOperand flags	Tom Stellard	2012-08-23	2	-8/+27
*	radeon/llvm: Add flag operand to some instructions	Tom Stellard	2012-08-23	7	-33/+97
*	radeon/llvm: Encapsulate setting of MachineOperand flags	Tom Stellard	2012-08-23	4	-50/+71
*	radeon/llvm: ExpandSpecialInstrs - Add support for cube instructions	Tom Stellard	2012-08-21	4	-63/+100
*	radeon/llvm: ExpandSpecialInstrs - Add support for vector instructions	Tom Stellard	2012-08-21	2	-15/+30
*	radeon/llvm: Add R600ExpandSpecialInstrs pass	Tom Stellard	2012-08-21	6	-14/+112
*	radeon/llvm: Add helper function for getting sub reg indices	Tom Stellard	2012-08-21	3	-6/+19
*	radeon-llvm: Start multithreaded before using llvm.	Mathias Fröhlich	2012-08-20	1	-0/+15
*	radeon/llvm: Lower implicit parameters before ISel	Tom Stellard	2012-08-16	3	-69/+42