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* r600g: make tgsi-to-llvm generates store.pixel* intrinsic for fsVincent Lejeune2012-11-021-0/+3
| | | | Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
* radeon/llvm: Add intrinsic for reading SI FRONT_FACE VGPR in the pixel shader.Michel Dänzer2012-10-262-0/+6
| | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: Sort tgsi opcode action initializationTom Stellard2012-10-191-59/+50
| | | | This was done in order to identify and remove duplicate entries.
* radeon/llvm: Fix lowering TGSI_OPCODE_SSGTom Stellard2012-10-191-1/+1
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* radeon/llvm: Fix build with LLVM 3.2Tom Stellard2012-10-111-3/+10
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* radeon/llvm: use ceil intrinsic instead of llvm.AMDIL.round.posinfVincent Lejeune2012-10-103-6/+2
| | | | Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: use floor intrinsic instead of llvm.AMDIL.floorVincent Lejeune2012-10-105-5/+5
| | | | Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: use llvm fabs intrinsicVincent Lejeune2012-10-103-6/+4
| | | | Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: use llvm intrinsic for flog2Vincent Lejeune2012-10-104-5/+4
| | | | Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: add support for cos/sin intrinsicVincent Lejeune2012-10-103-12/+15
| | | | Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: add a pattern for fsqrtVincent Lejeune2012-10-101-0/+3
| | | | Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: Disable SI flow control again for now.Michel Dänzer2012-10-021-1/+2
| | | | | | | It makes piglit unreliable due to VM protection faults and GPU lockups. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: Only initialize the AMDGPU targetTom Stellard2012-10-011-7/+1
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* radeon: Fix build with LLVM 3.1Tom Stellard2012-10-011-0/+1
| | | | The build was broken by commit 8d9778589f4b3a174e884338adb0fe1bdeca5eb7
* radeon: Support LLVM 3.2Tom Stellard2012-10-013-3/+11
| | | | | LLVM 3.2 and newer requires that the R600/SI backend be part of the LLVM tree.
* r600g: add some members to radeon_llvm_contextVincent Lejeune2012-09-281-0/+6
| | | | Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: improve select_cc lowering to generate CND* more oftenVincent Lejeune2012-09-273-41/+88
| | | | | | | | v2: - Simplify isZero() - Remove a unused function prototype - Clean whitespace trails Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: Fix instruction encoding for r600 family GPUsTom Stellard2012-09-243-15/+14
| | | | | | Tested-by: Michel Dänzer <[email protected]> https://bugs.freedesktop.org/show_bug.cgi?id=55217
* radeon/llvm: support for interpolation intrinsicsVincent Lejeune2012-09-2210-2/+318
| | | | Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: Handle loads from the constants address space.Tom Stellard2012-09-212-0/+10
| | | | | Reading from constant memory is not supported yet, so constant reads use global memory.
* radeon/llvm: Add support for v4f32 stores on R600Tom Stellard2012-09-213-9/+27
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* radeon/llvm: Add support for i8 reads on R600Tom Stellard2012-09-213-0/+25
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* radeon/llvm: Expand vector fadd and fmul on R600Tom Stellard2012-09-211-0/+3
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* radeon/llvm: Add optimization for FP_ROUNDTom Stellard2012-09-212-0/+27
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* radeon/llvm: Replace AMDGPU pow intrinsic with the llvm versionTom Stellard2012-09-214-7/+26
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* radeon/llvm: Emit ISA for ALU instructions in the R600 code emitterMichal Sciubidlo2012-09-195-139/+238
| | | | Signed-off-by: Tom Stellard <[email protected]>
* radeon/llvm: Only support 512 constant registers on R600Tom Stellard2012-09-191-1/+1
| | | | | This is necessary upcoming encoding changes, since we will only be using 9-bits for register encoding.
* radeon/llvm: Add a fdiv pattern.Vincent Lejeune2012-09-181-3/+10
| | | | Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
* radeon/llvm: reserve also corresponding 128bits regVincent Lejeune2012-09-181-0/+1
| | | | Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
* radeon/llvm: Inital flow control support for SITom Stellard2012-09-177-2/+168
| | | | | | This adds basic flow control support for If-Then-Else blocks using predicates (stored in the EXEC register) and a predicate stack for nested flow control.
* radeon/llvm: Fix unused variable warningTom Stellard2012-09-171-1/+0
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* radeon/llvm: Move kernel arg lowering into R600TargetLowering classTom Stellard2012-09-176-470/+35
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* radeon/llvm: Match integer add/sub for SI.Michel Dänzer2012-09-171-2/+8
| | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: Complete integer comparison patterns for SI.Michel Dänzer2012-09-171-4/+12
| | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: Match AMDGPUfract on SI.Michel Dänzer2012-09-171-1/+3
| | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: Match int_AMDGPU_floor for SI.Michel Dänzer2012-09-171-1/+3
| | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: Match vector logical operations on SI.Michel Dänzer2012-09-171-3/+9
| | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: Support frint on SIChristian König2012-09-141-1/+3
| | | | | | | | Gets VDPAUs shaders working again. Signed-off-by: Christian König <[email protected]> Reviewed-by: Tom Stellard <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeon/llvm: Fix lowering of vbuildTom Stellard2012-09-137-93/+19
| | | | | | Some of the old AMDIL code was hard-coding subreg indices when creating the VBUILD node, which was making it difficult to match the vector_insert patterns.
* radeon/llvm: Support fmul on SITom Stellard2012-09-131-1/+4
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* radeon/llvm: Fix operand order of V_CNDMASK in custom inserterTom Stellard2012-09-111-1/+1
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeon/llvm: Assert if we try to encode an unknown registerTom Stellard2012-09-111-1/+1
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeon/llvm: Add register encoding for VCCTom Stellard2012-09-111-0/+1
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeon/llvm: Ignore special registers when calculating reg countTom Stellard2012-09-111-0/+2
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: Handle position input parameter for pixel shaders v2Tom Stellard2012-09-112-0/+22
| | | | | | | | v2: - Don't increment ninterp or set any of the have_* flags for TGSI_SEMANTIC_POSITION Reviewed-by: Michel Dänzer <[email protected]>
* radeon/llvm: Coding style fixesTom Stellard2012-09-114-31/+31
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: Move interpolation mode check into the compilerTom Stellard2012-09-111-1/+12
| | | | | | | The compiler needs to know which interpolation modes are enabled, so it knows which values will be preloaded into the VGPRs. Reviewed-by: Michel Dänzer <[email protected]>
* radeon/llvm: Add SHADER_TYPE instructionTom Stellard2012-09-118-1/+32
| | | | | | | This allows the program to specify the type of shader being compiled (e.g. PXEL, VERTEX, etc.) Reviewed-by: Michel Dänzer <[email protected]>
* radeon/llvm: Match fexp2 for SI.Michel Dänzer2012-09-071-1/+3
| | | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: Add intrinsic for enabling whole quad mode in SI pixel shaders.Michel Dänzer2012-09-064-0/+23
| | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
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