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* radeon/llvm: Lower store_output intrinsic during DAG loweringTom Stellard2012-08-153-22/+22
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* radeon/llvm: Force VTX_READ instructions to use same reg for src and dstTom Stellard2012-08-151-0/+14
| | | | | | I was seeing some GPU hangs that seemed to be cause by ALU instructions writing to the same register used as the source for VTX_READ. Adding this constraint to the VTX_READ instructions avoids this situation.
* radeon/llvm: Inline immediate offset when lowering implicit parametersTom Stellard2012-08-141-4/+8
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* radeon/llvm: Use correct opcocde for BREAK_LOGICALNZ_i32Tom Stellard2012-08-141-1/+4
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* radeon/llvm: Add $(LLVM_LDFLAGS) to the loader linker flagsTom Stellard2012-08-021-1/+1
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* radeon/llvm: Add support for more f32 CMP instructions on SITom Stellard2012-08-021-5/+15
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* radeon/llvm: Add support for fneg on SITom Stellard2012-08-022-0/+16
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* radeon/llvm: Add support for fp_to_sint on SITom Stellard2012-08-021-1/+3
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* radeon/llvm: Remove CMOVLOG DAG nodeTom Stellard2012-08-026-75/+9
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* radeonsi: Handle TGSI DIV opcode.Michel Dänzer2012-08-021-0/+5
| | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: fix fp immediates on SIChristian König2012-08-021-7/+20
| | | | | | | | I don't know if this is a good idea, but it fixes the problem at hand. Signed-off-by: Christian König <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: fix calculation of max register numberChristian König2012-08-011-1/+1
| | | | | Signed-off-by: Christian König <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: Add pseudo-support for 64-bit immediate types on SITom Stellard2012-07-312-0/+23
| | | | | | | | SI does not support 64-bit immediates natively, but llvm will generate i64 immediates when indexing loads and stores (since SI has 64-bit pointers). The i64 indices will always be small enough to fit into 32-bits (i.e. the high 32 bits will always be all zeros), so we can treat these index values as 32-bits.
* radeon/llvm: Fix incorrect return value in SelectADDRReg()Tom Stellard2012-07-311-1/+1
| | | | We need to return true when we match the pattern.
* radeon/llvm: Move SMRD IMM pattern before SMRD SGPR patternTom Stellard2012-07-311-7/+6
| | | | | | | In tablegen, if two patterns match, the one that comes first in the file is given preference. We want the SMRD IMM pattern to be given preference, because it encodes the pointer offset in its immediate field, which saves us an add instruction.
* radeon/llvm: Cleanup AMDIL.hTom Stellard2012-07-304-91/+26
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* radeon/llvm: Rename all AMDIL* classes to AMDGPU*Tom Stellard2012-07-3030-496/+496
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* radeon/llvm: Merge AMDILSubtarget into AMDGPUSubtargetTom Stellard2012-07-3025-324/+156
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* radeon/llvm: Merge AMDILTargetLowering class into AMDGPUTargetLoweringTom Stellard2012-07-3011-241/+144
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* radeon/llvm: Remove IL_cmp DAG nodeTom Stellard2012-07-304-502/+2
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* radeon/llvm: Cleanup and reorganize AMDIL .td filesTom Stellard2012-07-3013-2303/+335
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* radeon/llvm: Remove lowering code for unsupported featuresTom Stellard2012-07-308-805/+50
| | | | e.g. function calls, load/store from stack
* radeon/llvm: Remove AMDILVersion.tdTom Stellard2012-07-302-59/+0
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* radeon/llvm: Remove AMDILAlgorithms.tppTom Stellard2012-07-302-94/+19
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* radeon/llvm: Merge AMDILInstrInfo.cpp into AMDGPUInstrInfo.cppTom Stellard2012-07-3012-693/+512
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* radeon/llvm: Merge AMDILRegisterInfo into AMDGPURegisterInfoTom Stellard2012-07-3012-283/+69
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* radeon/llvm: Change the tablegen target from AMDIL to AMDGPUTom Stellard2012-07-3014-107/+119
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* radeon/llvm: Add instruction defs for branches on SITom Stellard2012-07-273-17/+126
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* radeon/llvm: Fix VOPC and V_CNDMASK encodingTom Stellard2012-07-274-10/+13
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* radeon/llvm: Assert if we try to copy SCC regTom Stellard2012-07-271-0/+6
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* radeon/llvm: Add SI DAG optimizations for setcc, select_ccTom Stellard2012-07-272-0/+54
| | | | | These are needed for correctly lowering branch instructions in some cases.
* radeon/llvm: Add support for encoding SI branch instructionsTom Stellard2012-07-271-15/+35
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* radeon/llvm: Add special nodes for SALU operations on VCCTom Stellard2012-07-276-1/+89
| | | | | | | The VCC register is tricky because the SALU views it as 64-bit, but the VALU views it as 1-bit. In order to deal with this we've added some special bitcast and binary operations to help convert from the 64-bit SALU view to the 1-bit VALU view and vice versa.
* radeon/llvm: Add i1 registers for SI.Tom Stellard2012-07-271-0/+2
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* radeon/llvm: Fix CCReg definitions on SITom Stellard2012-07-272-3/+10
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* radeon/llvm: Add bitconvert patterns for SITom Stellard2012-07-271-0/+6
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* radeon/llvm: Add custom lowering for SELECT_CC nodes on SITom Stellard2012-07-272-0/+20
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* radeon/llvm: Move conditional pattern leafs to common tablegen fileTom Stellard2012-07-272-41/+41
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* radeon/llvm: Implement getSetCCResultType for SITom Stellard2012-07-272-0/+6
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* radeon/llvm: Custom lower BR_CC for SITom Stellard2012-07-272-0/+41
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* radeon/llvm: Move lowering of BR_CC node to R600ISelLoweringTom Stellard2012-07-274-31/+31
| | | | | SI will handle BR_CC different from R600, so we need to move it out of the shared instruction selector.
* radeon/llvm: Move lowering of SETCC node to R600ISelLoweringTom Stellard2012-07-274-38/+29
| | | | | SI will handle SETCC different from R600, so we need to move it out of the shared instruction selector.
* radeon/llvm: Use correct node type when lowering SETCCTom Stellard2012-07-271-0/+1
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* radeon/llvm: Move LowerSELECT_CC into R600ISelLoweringTom Stellard2012-07-274-111/+112
| | | | | SI will handle SELECT_CC different from R600, so we need to move it out of the shared instruction selector.
* radeon/llvm: Fix a bug with IF LOGICALNZ with int operandVincent Lejeune2012-07-232-3/+5
| | | | Signed-off-by: Tom Stellard <[email protected]>
* radeon/llvm: Fix CR/LF in AMDILSIDevice.hAndreas Boll2012-07-131-1/+1
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* radeon/llvm: Clean up AMDILIntrinsicInfo.cppTom Stellard2012-07-132-84/+5
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* radeon/llvm: Coding style fixesTom Stellard2012-07-132-409/+325
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* radeon/llvm: Don't use lp_build_swizzle_aos() for swizzlesTom Stellard2012-07-121-8/+13
| | | | | | | This function assumes that lp_build_context::type is a vector type, which is not true for r600 or radeonsi. This fixes an assertion failure using glamor 2D accel.
* radeon/llvm: Use multiclasses for floating point loadsTom Stellard2012-07-117-50/+46
| | | | | | | The original strategy for handling floating point loads, which was to lower (f32 load) to (f32 bitcast (i32 load)) wasn't really working. The main problem was that the DAG legalizer couldn't handle replacing a node with two results (load) with a node with only one result (bitcast).
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