summaryrefslogtreecommitdiffstats
path: root/src/gallium/drivers/radeon
Commit message (Collapse)AuthorAgeFilesLines
* radeon/uvd: handle HEVC main 10 decodeBoyuan Zhang2016-03-111-11/+58
| | | | | Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: Lazily re-set sampler views after disabling DCCBas Nieuwenhuizen2016-03-111-2/+0
| | | | | | | | | | Clear DCC flags if necessary when binding a new sampler view. v2: Do not reset DCC flags of bound sampler views. v3: Check that we have a real texture (Nicolai) Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: notify all contexts when cmasks are enabled/disabledNicolai Hähnle2016-03-102-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There is an annoying corner case that I stumbled across while looking into piglit's arb_shader_image_load_store/execution/load-from-cleared-image.shader_test (which can be easily adapted to demonstrate the bug without the ARB_shader_image_load_store extension) When we bind a texture and then clear it using glClear (by attaching it to the current framebuffer) for the first time, we allocate a separate cmask for the texture to do fast clear, but the corresponding bit in compressed_colortex_mask is not set. Subsequent rendering will use incorrect data. Conversely, when a currently bound texture with an existing cmask is exported leading to that cmask being disabled, the compressed_colortex_mask bit will remain set, leading to an assertion later on in debug builds. Since iterating through all contexts and/or remembering where every texture is bound would be costly, and cmask enable/disable should be rare, we will maintain a global counter to signal contexts that they must update their compressed_colortex_masks. This patch introduces the global counter, and subsequent patches will do the mask update. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: use explicit drm_major, drm_minor checkEmil Velikov2016-03-091-1/+2
| | | | | | | | | | Just like everywhere else in the radeon codebase. v2: Don't forget about drm_major == 3 (Alex) Cc: Alex Deucher <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: get PCI infoMarek Olšák2016-03-091-0/+6
| | | | | | | | | This will be queried by the OpenCL stack using an interop call. I have tested that the values match lspci. Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: set amdgpu metadata before exporting a textureMarek Olšák2016-03-092-0/+10
| | | | | Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: disable DCC on handle export if expecting write accessMarek Olšák2016-03-092-0/+36
| | | | | | | This should be okay except that sampler views and images are not re-set. Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: allocate DCC in the same backing buffer as the textureMarek Olšák2016-03-092-30/+23
| | | | | | | To allow sharing textures with DCC enabled. Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: disable CMASK on handle export if sharing doesn't allow it (v2)Marek Olšák2016-03-092-0/+42
| | | | | | | v2: remove the list of all contexts Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: eliminate fast color clear before sharingMarek Olšák2016-03-091-0/+16
| | | | | Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: don't use fast color clear if sharing doesn't allow itMarek Olšák2016-03-091-0/+8
| | | | | Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: disallow handle export for MSAA & depth texturesMarek Olšák2016-03-091-0/+7
| | | | | Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: remember that texture_from_handle was called and its flagsMarek Olšák2016-03-091-2/+9
| | | | | Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: check that handle usage doesn't change for a resourceMarek Olšák2016-03-092-0/+4
| | | | | Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: disallow reallocation of shared buffersMarek Olšák2016-03-091-0/+4
| | | | | Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: if we can't discard a whole resource, discard the range insteadMarek Olšák2016-03-091-5/+9
| | | | | Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: buffer valid range tracking only works with unshared buffersMarek Olšák2016-03-091-0/+1
| | | | | Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: don't set texture metadata for buffersMarek Olšák2016-03-091-2/+5
| | | | | Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: set texture metadata only onceMarek Olšák2016-03-093-2/+9
| | | | | Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: clean up r600_texture_get_handleMarek Olšák2016-03-091-7/+7
| | | | | Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: move code initializing texture metadata to its own functionMarek Olšák2016-03-091-15/+23
| | | | | Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: allow drivers to set/get opaque metadataMarek Olšák2016-03-091-0/+10
| | | | | Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: rename winsys buffer_get/set_tiling to buffer_get/set_metadataMarek Olšák2016-03-092-6/+6
| | | | | Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: remove rcs parameter from radeon_winsys::buffer_set_tilingMarek Olšák2016-03-092-3/+1
| | | | | | | | This was needed for DRM < 2.12.0 where the kernel was rewriting tiling flags in IBs. Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: use a structure for passing tiling flags from/to winsysMarek Olšák2016-03-092-51/+51
| | | | | | | and call it radeon_bo_metadata Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium: add external usage flags to resource_from(get)_handle (v2)Marek Olšák2016-03-091-2/+4
| | | | | | | | | This will allow drivers to make better decisions about texture sharing for DRI2, DRI3, Wayland, and OpenCL. v2: add read/write flags, take advantage of __DRI_IMAGE_USE_BACKBUFFER Reviewed-by: Axel Davy <[email protected]>
* radeon/uvd: increase max height to 4096 for VI and newerTamil velan2016-03-081-1/+1
| | | | | | | | | | | | | | | | | With this issue 'mpv --hwdec=vdpau --vo=vdpau <stream>' fails for vdpau decode if the stream height is 4096. Vdpau decode of height upto 4096 is necessary usecase on amdgpu driver for VI and newer platforms. The fix is in driver specific implementation of "Decoder Query Capabilities" API to return 4096 for VI and newer platforms. With this fix vdpauinfo reports height support as 4096 and mpv for vdpau decode works fine for 4096 height streams. Signed-off-by: Tamil velan <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Cc: "11.1 11.2" <[email protected]>
* gallium/radeon: don't use temporary buffers for persistent mappingsMarek Olšák2016-03-081-2/+4
| | | | | Cc: 11.1 11.2 <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeon/uvd: disable MPEG1Christian König2016-03-081-0/+1
| | | | | | | | The hardware simply doesn't support that correctly. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Cc: "11.1 11.2" <[email protected]>
* winsys/radeon: drop support for DRM 2.12.0 (kernel < 3.2)Marek Olšák2016-03-011-15/+1
| | | | | | | | | | | | | | in order to make some winsys interface changes easier This distros should use new DRM if they want to use new Mesa: Distro kernel mesa eol SLES 10 2.6.16 6.4.2 2016-07 SLED 11 3.0 9.0.3 2022-03 RHEL 5 2.6.18 6.5.1 2017-03 RHEL 6 2.6.32 10.4.3 2020-11 Debian 6 2.6.32 7.7.1 2016-02 Reviewed-by: Michel Dänzer <[email protected]>
* gallium/radeon: Add space between string literal and identifierRob Herring2016-02-291-1/+1
| | | | | | | | | | | | | Fix compiles with clang that have this C++11 error: src/gallium/drivers/radeon/r600_pipe_common.h:662:34: error: invalid suffix on literal; C++11 requires a space between literal and identifier [-Wreserved-user-defined-literal] Cc: "11.1 11.2" <[email protected]> Cc: Marek Olšák <[email protected]> Signed-off-by: Rob Herring <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* gallium/radeon: disable evergreen_do_fast_color_clear for BEOded Gabbay2016-02-291-0/+5
| | | | | | | | | | | | | | | | This function is currently broken for BE. I assume it's because of util_pack_color(). Until I fix this path, I prefer to disable it so users would be able to see correct colors on their desktop and applications. Together with the two following patches: - gallium/r600: Don't let h/w do endian swap for colorformat - gallium/radeon: remove separate BE path in r600_translate_colorswap it fixes BZ#72877 and BZ#92039 Signed-off-by: Oded Gabbay <[email protected]> Cc: "11.1 11.2" <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: remove separate BE path in r600_translate_colorswapOded Gabbay2016-02-291-12/+1
| | | | | | | | | | | | | | | | | | | | After further testing, it appears there is no need for separate BE path in r600_translate_colorswap() The only fix remaining is the change of the last if statement, in the 4 channels case. Originally, it contained an invalid swizzle configuration that never got hit, in LE or BE. So the fix is relevant for both systems. This patch adds an additional 120 available visuals for LE and BE, as seen in glxinfo v2: Tested for regressions by running piglit gpu.py with CAICOS (r600g) on x86-64 machine. No regressions found. Signed-off-by: Oded Gabbay <[email protected]> Cc: "11.1 11.2" <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: return correct values for BE in r600_translate_colorswapOded Gabbay2016-02-251-4/+4
| | | | | | | | | | | | | | | Because I changed the swizzle check, I also need to adapt the return values for each check. It's basically almost the same as before, we just cross between STD and STD_REV, and cross between ALT and ALT_REV This fixes the rgba test in gl-1.0-readpixsanity (piglit) and also fixes tri-flat (mesa demos). Signed-off-by: Oded Gabbay <[email protected]> Cc: "11.1 11.2" <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: Correctly translate colorswaps for big endianOded Gabbay2016-02-231-0/+11
| | | | | | | | | | | | | | | | | | | | | | The current code in r600_translate_colorswap uses the swizzle information to determine which colorswap to use. This works for BE & LE when the nr_channels is <4, but when nr_channels==4 (e.g. PIPE_FORMAT_A8R8G8B8_UNORM), this method can not be used for both BE and LE, because the swizzle info is the same for both of them. As a result, r600g doesn't support 24bit color formats, only 16bit, which forces the user to choose 16bit color in X server. This patch fixes this bug by separating the checks for LE and BE and adapting the swizzle conditions in the BE part of the checks. Tested on an Evergreen GPU (Cedar GL FirePro 2270) running inside POWER7 Big-Endian Machine. Signed-off-by: Oded Gabbay <[email protected]> CC: "11.2" "11.1" <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: remove unused radeon_shader_binary_free_* functionsMarek Olšák2016-02-212-33/+0
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: make radeon_shader_reloc name string fixed-sizedMarek Olšák2016-02-212-6/+3
| | | | | | This will simplify implementations of binary shaders. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: enable compiling one variant per shaderMarek Olšák2016-02-212-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Shader stats from VERDE: Default scheduler: Totals: SGPRS: 491272 -> 488672 (-0.53 %) VGPRS: 289980 -> 311093 (7.28 %) Code Size: 11091656 -> 11219948 (1.16 %) bytes LDS: 97 -> 97 (0.00 %) blocks Scratch: 1732608 -> 2246656 (29.67 %) bytes per wave Max Waves: 78063 -> 77352 (-0.91 %) Wait states: 0 -> 0 (0.00 %) Looking at some of the worst regressions, I get: - The VGPR increase seems to be caused by the fact that if PS has used less than 16 VGPRs, now it will always use 16 VGPRs and sometimes even 20. However, the wave count remains at 10 if VGPRs <= 24, so no harm there. - The scratch increase seems to be caused by SGPR spilling. The unnecessary SGPR spilling has been an ongoing issue with the compiler and it's completely fixable by rematerializing s_loads or reordering instructions. SI scheduler: Totals: SGPRS: 374848 -> 374576 (-0.07 %) VGPRS: 284456 -> 307515 (8.11 %) Code Size: 11433068 -> 11535452 (0.90 %) bytes LDS: 97 -> 97 (0.00 %) blocks Scratch: 509952 -> 522240 (2.41 %) bytes per wave Max Waves: 79456 -> 78217 (-1.56 %) Wait states: 0 -> 0 (0.00 %) VGPRs - same story as before. The SI scheduler doesn't spill SGPRs so much and generally spills way less than the default scheduler. (522240 spills vs 2246656 spills) Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: add basic code for setting shader return valuesMarek Olšák2016-02-212-4/+14
| | | | | | LLVMBuildInsertValue will be used on return_value. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeon/llvm: Add TargetLibraryInfo to the pass managerTom Stellard2016-02-171-1/+7
| | | | | | | | This will prevent optimization passes from introducing unsupported library calls. Tested-by: Michel Dänzer <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeon/llvm: Set the target triple on the moduleTom Stellard2016-02-172-2/+10
| | | | | Tested-by: Michel Dänzer <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* Handle removal of LLVMAddTargetData in SVN revision 260919Matthew Dawson2016-02-161-0/+6
| | | | | | | | | | | | | | | | | | | LLVM removed LLVMAddTargetData for the 3.9 release in r260919. For the two places in mesa where this is called, only enable the lines when compiling for less then 3.9. For the radeon driver, I'm not sure how to check if any other LLVM calls need to be adjusted. I think since the target data used is extracted from the LLVMModule, it isn't necessary to pass it back to LLVM again. The code does compile, and at least for radeonsi does run OpenGL games. [ Michel Dänzer: Move #if closer to LLVMAddTargetData in lp_bld_init.c, and add HAVE_LLVM < 0x0309 guards around now unused occurrences of TD and data_layout ] Signed-off-by: Matthew Dawson <[email protected]> Reviewed-and-Tested-by: Michel Dänzer <[email protected]>
* gallium/radeon: drop support for LLVM 3.5Marek Olšák2016-02-111-6/+1
| | | | | | Reviewed-by: Nicolai Hähnle <[email protected]> v2: adjust the comment in the amdgpu winsys
* radeon/uvd: silence a warningMarek Olšák2016-02-101-0/+3
|
* gallium/radeon: add a function for adding llvm function attributesMarek Olšák2016-02-092-4/+10
| | | | | | This will be used for setting the new InitialPSInputAddr attribute. Reviewed-by: Nicolai Hähnle <[email protected]>
* r600g: Ignore format for PIPE_BUFFER targetsJan Vesely2016-02-051-1/+1
| | | | | | | | Fixes compute since 7dd31b81fee7fe40bd09cf3fbc324fcc32782479 gallium/radeon: support PIPE_CAP_SURFACE_REINTERPRET_BLOCKS Signed-off-by: Jan Vesely <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* gallium/radeon: implement query_memory_info (v2)Marek Olšák2016-02-051-0/+37
| | | | | | | v2: don't use DIV_ROUND_UP (no so useful) also return eviction stats Reviewed-by: Alex Deucher <[email protected]>
* gallium/radeon: remove radeon_info::r600_tiling_configMarek Olšák2016-02-052-2/+0
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* gallium/radeon: get pipe_interleave_bytes AKA group_bytes from the winsysMarek Olšák2016-02-054-64/+5
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* gallium/radeon: set num_banks in the winsysMarek Olšák2016-02-053-26/+2
| | | | | | | amdgpu doesn't have to set this, because radeonsi gets it from tile mode arrays by default. Reviewed-by: Michel Dänzer <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-26 01:01:26 +0000