| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | radeon/llvm: Add isMov() to AMDILInstrInfo | Tom Stellard | 2012-06-06 | 6 | -11/+34 |
| * | radeon/llvm: Remove deadcode from the AMDILISelLowering class | Tom Stellard | 2012-06-06 | 2 | -203/+0 |
| * | radeon/llvm: Don't lower RETURN to S_ENDPGM on SI | Tom Stellard | 2012-06-06 | 2 | -1/+4 |
| * | radeon/llvm: Remove AMDIL VCREATE* instructions | Tom Stellard | 2012-06-06 | 8 | -97/+12 |
| * | radeon/llvm: Remove AMDIL LOADCONST* instructions | Tom Stellard | 2012-06-06 | 13 | -322/+33 |
| * | radeon/llvm: Fix VTX_READ patterns | Tom Stellard | 2012-06-01 | 3 | -4/+33 |
| * | radeon/llvm: Emit 2 bytes for vertex fetch offsets | Tom Stellard | 2012-06-01 | 1 | -1/+1 |
| * | radeon/llvm: Only use indirect (vertex fetch) parameters for kernels | Tom Stellard | 2012-06-01 | 1 | -2/+6 |
| * | radeon/llvm: Eliminate CFGStructurizer dependency on AMDIL instructions | Tom Stellard | 2012-06-01 | 11 | -41/+124 |
| * | radeon/llvm: Change prefix on tablegen files to AMDGPU | Tom Stellard | 2012-06-01 | 17 | -50/+50 |
| * | radeon/llvm: Remove deadcode from the R600LowerInstructions pass | Tom Stellard | 2012-06-01 | 1 | -46/+2 |
| * | radeon/llvm: Remove AMDIL GLOBALSTORE* instructions | Tom Stellard | 2012-06-01 | 4 | -77/+36 |
| * | radeon/llvm: Remove AMDIL GLOBALLOAD* instructions | Tom Stellard | 2012-06-01 | 6 | -128/+24 |
| * | radeon/llvm: Update and fix some comments | Tom Stellard | 2012-05-29 | 2 | -12/+6 |
| * | radeonsi: Remove use.sgpr* intrinsics, use load instructions instead | Tom Stellard | 2012-05-29 | 4 | -30/+21 |
| * | radeonsi: Handle TGSI CONST registers | Tom Stellard | 2012-05-29 | 11 | -58/+171 |
| * | radeon/llvm: Remove AMDILIntrinsicInfo::GetDeclaration fuction body | Tom Stellard | 2012-05-29 | 1 | -20/+1 |
| * | radeon/llvm: Remove AMDILTargetMachine | Tom Stellard | 2012-05-29 | 19 | -363/+90 |
| * | radeon/llvm: Use a custom inserter for MASK_WRITE | Tom Stellard | 2012-05-25 | 4 | -34/+36 |
| * | radeon/llvm: Use tablegen pattern to lower bitconvert | Tom Stellard | 2012-05-25 | 4 | -294/+11 |
| * | radeon/llvm: Use a custom inserter to lower FNEG | Tom Stellard | 2012-05-25 | 5 | -22/+15 |
| * | radeon/llvm: Use a custom inserter to lower CLAMP | Tom Stellard | 2012-05-25 | 9 | -84/+41 |
| * | radeon/llvm: Use a custom inserter to lower FABS | Tom Stellard | 2012-05-25 | 10 | -42/+41 |
| * | radeon/llvm: add FLT_TO_UINT, UINT_TO_FLT instructions | Vadim Girlin | 2012-05-25 | 1 | -0/+20 |
| * | radeon/llvm: prepare to revert the round mode state to default | Vadim Girlin | 2012-05-25 | 1 | -2/+9 |
| * | radeon/llvm: fix opcode for RECIP_UINT_r600 | Vadim Girlin | 2012-05-25 | 1 | -1/+1 |
| * | radeon/llvm/loader: convert hardcoded gpu name to option | Vadim Girlin | 2012-05-25 | 1 | -2/+3 |
| * | radeon/llvm: Lower UDIV using the Selection DAG | Tom Stellard | 2012-05-24 | 8 | -212/+126 |
| * | radeon/llvm: Remove auto-generated AMDIL->ISA conversion code | Tom Stellard | 2012-05-24 | 14 | -280/+28 |
| * | radeon/llvm: Remove AMDIL instructions MULHI, SMUL | Tom Stellard | 2012-05-24 | 3 | -10/+5 |
| * | radeon/llvm: Remove AMDIL bitshift instructions (SHL, SHR, USHR) | Tom Stellard | 2012-05-24 | 8 | -693/+6 |
| * | radeon/llvm: Remove AMDIL FTOI and ITOF instructions | Tom Stellard | 2012-05-24 | 7 | -316/+7 |
| * | radeon/llvm: Remove AMDIL EXP* instructions | Tom Stellard | 2012-05-24 | 5 | -15/+7 |
| * | radeon/llvm: Remove AMDIL ADD instructions | Tom Stellard | 2012-05-24 | 6 | -179/+4 |
| * | radeon/llvm: Remove AMDIL binary instrutions (OR, AND, XOR, NOT) | Tom Stellard | 2012-05-24 | 8 | -422/+8 |
| * | radeon/llvm: Remove AMDILMachinePeephole pass | Tom Stellard | 2012-05-24 | 4 | -177/+0 |
| * | radeon/llvm: Remove AMDIL CMP instructions and associated lowering code | Tom Stellard | 2012-05-24 | 3 | -661/+22 |
| * | radeon/llvm: Remove AMDIL ROUND_NEAREST instruction | Tom Stellard | 2012-05-24 | 4 | -6/+6 |
| * | radeon/llvm: Remove AMDIL ROUND_POSINF instruction | Tom Stellard | 2012-05-24 | 4 | -6/+10 |
| * | radeon/llvm: Add custom SDNode for FRACT | Tom Stellard | 2012-05-24 | 6 | -6/+10 |
| * | radeon/llvm: Use -1 as true value for SET* integer instructions | Tom Stellard | 2012-05-24 | 3 | -32/+28 |
| * | radeon/llvm: Handle SETGE_INT, SETGE_UINT, and SETGT_UINT opcodes | Tom Stellard | 2012-05-24 | 1 | -0/+6 |
| * | radeon/llvm: Avoid error with SI in EmitInstrWithCustomInserter() | Tom Stellard | 2012-05-24 | 1 | -0/+1 |
| * | radeon/llvm: Handle selectcc DAG node | Tom Stellard | 2012-05-20 | 7 | -54/+350 |
| * | radeon/llvm: Fix segfault while lowering lrp intrinsic | Tom Stellard | 2012-05-17 | 1 | -2/+3 |
| * | radeon/llvm: Add DAG nodes for MIN instructions | Tom Stellard | 2012-05-17 | 6 | -14/+38 |
| * | radeon/llvm: Lower lrp intrinsic during ISel | Tom Stellard | 2012-05-17 | 3 | -7/+19 |
| * | radeon/llvm: Remove AMDIL MAD instruction defs | Tom Stellard | 2012-05-17 | 6 | -7/+14 |
| * | radeon/llvm: Remove AMDIL MUL_IEEE* instructions | Tom Stellard | 2012-05-17 | 3 | -7/+3 |
| * | radeon/llvm: Expand fsub during ISel | Tom Stellard | 2012-05-17 | 2 | -11/+2 |
