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* radeon/llvm: Fix lowering TGSI_OPCODE_SSGTom Stellard2012-10-191-1/+1
* radeon/llvm: Fix build with LLVM 3.2Tom Stellard2012-10-111-3/+10
* radeon/llvm: use ceil intrinsic instead of llvm.AMDIL.round.posinfVincent Lejeune2012-10-103-6/+2
* radeon/llvm: use floor intrinsic instead of llvm.AMDIL.floorVincent Lejeune2012-10-105-5/+5
* radeon/llvm: use llvm fabs intrinsicVincent Lejeune2012-10-103-6/+4
* radeon/llvm: use llvm intrinsic for flog2Vincent Lejeune2012-10-104-5/+4
* radeon/llvm: add support for cos/sin intrinsicVincent Lejeune2012-10-103-12/+15
* radeon/llvm: add a pattern for fsqrtVincent Lejeune2012-10-101-0/+3
* radeon/llvm: Disable SI flow control again for now.Michel Dänzer2012-10-021-1/+2
* radeon/llvm: Only initialize the AMDGPU targetTom Stellard2012-10-011-7/+1
* radeon: Fix build with LLVM 3.1Tom Stellard2012-10-011-0/+1
* radeon: Support LLVM 3.2Tom Stellard2012-10-013-3/+11
* r600g: add some members to radeon_llvm_contextVincent Lejeune2012-09-281-0/+6
* radeon/llvm: improve select_cc lowering to generate CND* more oftenVincent Lejeune2012-09-273-41/+88
* radeon/llvm: Fix instruction encoding for r600 family GPUsTom Stellard2012-09-243-15/+14
* radeon/llvm: support for interpolation intrinsicsVincent Lejeune2012-09-2210-2/+318
* radeon/llvm: Handle loads from the constants address space.Tom Stellard2012-09-212-0/+10
* radeon/llvm: Add support for v4f32 stores on R600Tom Stellard2012-09-213-9/+27
* radeon/llvm: Add support for i8 reads on R600Tom Stellard2012-09-213-0/+25
* radeon/llvm: Expand vector fadd and fmul on R600Tom Stellard2012-09-211-0/+3
* radeon/llvm: Add optimization for FP_ROUNDTom Stellard2012-09-212-0/+27
* radeon/llvm: Replace AMDGPU pow intrinsic with the llvm versionTom Stellard2012-09-214-7/+26
* radeon/llvm: Emit ISA for ALU instructions in the R600 code emitterMichal Sciubidlo2012-09-195-139/+238
* radeon/llvm: Only support 512 constant registers on R600Tom Stellard2012-09-191-1/+1
* radeon/llvm: Add a fdiv pattern.Vincent Lejeune2012-09-181-3/+10
* radeon/llvm: reserve also corresponding 128bits regVincent Lejeune2012-09-181-0/+1
* radeon/llvm: Inital flow control support for SITom Stellard2012-09-177-2/+168
* radeon/llvm: Fix unused variable warningTom Stellard2012-09-171-1/+0
* radeon/llvm: Move kernel arg lowering into R600TargetLowering classTom Stellard2012-09-176-470/+35
* radeon/llvm: Match integer add/sub for SI.Michel Dänzer2012-09-171-2/+8
* radeon/llvm: Complete integer comparison patterns for SI.Michel Dänzer2012-09-171-4/+12
* radeon/llvm: Match AMDGPUfract on SI.Michel Dänzer2012-09-171-1/+3
* radeon/llvm: Match int_AMDGPU_floor for SI.Michel Dänzer2012-09-171-1/+3
* radeon/llvm: Match vector logical operations on SI.Michel Dänzer2012-09-171-3/+9
* radeon/llvm: Support frint on SIChristian König2012-09-141-1/+3
* radeon/llvm: Fix lowering of vbuildTom Stellard2012-09-137-93/+19
* radeon/llvm: Support fmul on SITom Stellard2012-09-131-1/+4
* radeon/llvm: Fix operand order of V_CNDMASK in custom inserterTom Stellard2012-09-111-1/+1
* radeon/llvm: Assert if we try to encode an unknown registerTom Stellard2012-09-111-1/+1
* radeon/llvm: Add register encoding for VCCTom Stellard2012-09-111-0/+1
* radeon/llvm: Ignore special registers when calculating reg countTom Stellard2012-09-111-0/+2
* radeonsi: Handle position input parameter for pixel shaders v2Tom Stellard2012-09-112-0/+22
* radeon/llvm: Coding style fixesTom Stellard2012-09-114-31/+31
* radeonsi: Move interpolation mode check into the compilerTom Stellard2012-09-111-1/+12
* radeon/llvm: Add SHADER_TYPE instructionTom Stellard2012-09-118-1/+32
* radeon/llvm: Match fexp2 for SI.Michel Dänzer2012-09-071-1/+3
* radeon/llvm: Add intrinsic for enabling whole quad mode in SI pixel shaders.Michel Dänzer2012-09-064-0/+23
* radeon/llvm: SI shader vector instructions implicitly use the EXEC register.Michel Dänzer2012-09-061-0/+4
* radeon/llvm: Extend SI EXEC register support.Michel Dänzer2012-09-062-2/+7
* radeon/llvm: Remove R600InstrInfo.td from TD_FILESTom Stellard2012-09-061-1/+0
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