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* radeon/llvm: Fix a bug with IF LOGICALNZ with int operandVincent Lejeune2012-07-232-3/+5
| | | | Signed-off-by: Tom Stellard <[email protected]>
* radeon/llvm: Fix CR/LF in AMDILSIDevice.hAndreas Boll2012-07-131-1/+1
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* radeon/llvm: Clean up AMDILIntrinsicInfo.cppTom Stellard2012-07-132-84/+5
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* radeon/llvm: Coding style fixesTom Stellard2012-07-132-409/+325
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* radeon/llvm: Don't use lp_build_swizzle_aos() for swizzlesTom Stellard2012-07-121-8/+13
| | | | | | | This function assumes that lp_build_context::type is a vector type, which is not true for r600 or radeonsi. This fixes an assertion failure using glamor 2D accel.
* radeon/llvm: Use multiclasses for floating point loadsTom Stellard2012-07-117-50/+46
| | | | | | | The original strategy for handling floating point loads, which was to lower (f32 load) to (f32 bitcast (i32 load)) wasn't really working. The main problem was that the DAG legalizer couldn't handle replacing a node with two results (load) with a node with only one result (bitcast).
* radeon/llvm: Don't set the IMM bit in SMRD instruction definitions.Tom Stellard2012-07-111-7/+2
| | | | The IMM bit is already being set in SICodeEmitter.
* radeon/llvm: Rename namespace from AMDIL to AMDGPUTom Stellard2012-07-0925-360/+361
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* radeon/llvm: Enable vec4 loads on R600Tom Stellard2012-06-293-0/+20
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* radeon/llvm: Enable floating point stores on R600Tom Stellard2012-06-291-0/+6
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* radeon/llvm: Handle floating point loads on R600Tom Stellard2012-06-292-0/+31
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* radeon/llvm: Expand UDIV and UREM nodesTom Stellard2012-06-291-4/+3
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* radeon/llvm: Emit raw ISA for vertex fetch instructionsTom Stellard2012-06-292-61/+99
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* radeon/llvm: Turn on the BitExtract peephole optimizationTom Stellard2012-06-212-5/+32
| | | | | Thie BitExtract optimization folds a mask and shift operation together into a single instruction (BFE_UINT).
* radeon/llvm: Lower ROTL to BIT_ALIGNTom Stellard2012-06-216-1/+54
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* radeon/llvm: Use the VLIW Scheduler for R600->NITom Stellard2012-06-2112-8/+75
| | | | | | | | | | | | | | | | | | | It's not optimal, but it's better than the register pressure scheduler that was previously being used. The VLIW scheduler currently ignores all the complicated instruction groups restrictions and just tries to fill the instruction groups with as many instructions as possible. Though, it does know enough not to put two trans only instructions in the same group. We are able to ignore the instruction group restrictions in the LLVM backend, because the finalizer in r600_asm.c will fix any illegal instruction groups the backend generates. Enabling the VLIW scheduler improved the run time for a sha1 compute shader by about 50%. I'm not sure what the impact will be for graphics shaders. I tested Lightsmark with the VLIW scheduler enabled and the framerate was about the same, but it might help apps that use really big shaders.
* radeon/llvm: Fix CR/LF in Processors.tdTörök Edwin2012-06-191-17/+17
| | | | Signed-off-by: Tom Stellard <[email protected]>
* radeon/llvm: Fix sin/cos codegen on R700Török Edwin2012-06-191-19/+24
| | | | | | | | | | Based on https://bugs.freedesktop.org/show_bug.cgi?id=50317#c4 Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=50316 https://bugs.freedesktop.org/show_bug.cgi?id=50317 Signed-off-by: Tom Stellard <[email protected]>
* radeon/llvm: Update comment in AMDGPU.tdTom Stellard2012-06-181-2/+3
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* radeon/llvm: Remove unused AMDIL TableGen definitonsTom Stellard2012-06-1818-6140/+26
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* radeon/llvm: Eliminate getRegClassFromType() functionTom Stellard2012-06-181-42/+1
| | | | We can use TargetLowering::getRegClassFor() instead.
* radeon/llvm: Remove deadcode from AMDILISelLowering.cppTom Stellard2012-06-184-1687/+0
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* radeonsi: Handle SUB_f32.Thomas Stellard2012-06-122-2/+3
| | | | | Signed-off-by: Thomas Stellard <[email protected]> Signed-off-by: Michel Dänzer <[email protected]>
* radeonsi: Only dump shaders with environment variable RADEON_DUMP_SHADERS=1.Michel Dänzer2012-06-121-1/+5
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* automake: Globally add stub automake targets to the old Makefiles.Eric Anholt2012-06-111-3/+0
| | | | | | | | | I tried to update all the old Makefiles that included the default config to be sure they had a default target if they didn't previously have one, since this new all target will always point at it. Almost everything had one. Reviewed-by: Kenneth Graunke <[email protected]>
* radeon/llvm: Emulate RECIP_UINT instruction on CaymanTom Stellard2012-06-062-4/+13
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* radeon/llvm: Remove some duplicate code in the R600 CodeEmitterTom Stellard2012-06-061-9/+3
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* radeon/llvm: Fix MULLO* instructions on CaymanTom Stellard2012-06-064-14/+53
| | | | | On Cayman, the MULLO* instructions must fill all slots in an instruction group.
* r600g: Compute support for CaymanTom Stellard2012-06-061-48/+44
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* radeon/llvm: Remove obselete hooks for the ConvertToISA passTom Stellard2012-06-066-87/+1
| | | | | | We can't remove this pass yet, because we need it to convert AMDIL registers in BRANCH* instructions, but we don't need it for instruction conversion any more.
* radeon/llvm: Remove AMDIL MOVE* instructionsTom Stellard2012-06-065-20/+2
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* radeon/llvm: Add isMov() to AMDILInstrInfoTom Stellard2012-06-066-11/+34
| | | | | This enables the CFGStructurizer to work without the AMDIL::MOV* instructions.
* radeon/llvm: Remove deadcode from the AMDILISelLowering classTom Stellard2012-06-062-203/+0
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* radeon/llvm: Don't lower RETURN to S_ENDPGM on SITom Stellard2012-06-062-1/+4
| | | | | Instead create an S_ENDPGM instruction in the CodeEmitter and emit it after all the other instructions.
* radeon/llvm: Remove AMDIL VCREATE* instructionsTom Stellard2012-06-068-97/+12
| | | | This obsoletes the AMDGPULowerInstruction pass.
* radeon/llvm: Remove AMDIL LOADCONST* instructionsTom Stellard2012-06-0613-322/+33
| | | | This obsoletes the R600LowerInstruction and SIPropagateImmReads passes.
* radeon/llvm: Fix VTX_READ patternsTom Stellard2012-06-013-4/+33
| | | | | | | | | The VTX_READ instructions were using the ADDRParam ComplexPattern which allows a load instruction's offset to be a register, but VTX_READ instructions can only handle an immediate offset. Also, the load_param pattern fragment had an erroneous return true; statement that was causing it to match the wrong load instructions.
* radeon/llvm: Emit 2 bytes for vertex fetch offsetsTom Stellard2012-06-011-1/+1
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* radeon/llvm: Only use indirect (vertex fetch) parameters for kernelsTom Stellard2012-06-011-2/+6
| | | | | | Kernel parameters can only be retrieved via vertex fetchs. Direct parameters (i.e parameters stored in the constant buffer) are not supported yet.
* radeon/llvm: Eliminate CFGStructurizer dependency on AMDIL instructionsTom Stellard2012-06-0111-41/+124
| | | | | | Add some hooks to the R600,SI InstrInfo and RegisterInfo classes, so that the CFGStructurizer pass can run without any relying on AMDIL instructions.
* radeon/llvm: Change prefix on tablegen files to AMDGPUTom Stellard2012-06-0117-50/+50
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* radeon/llvm: Remove deadcode from the R600LowerInstructions passTom Stellard2012-06-011-46/+2
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* radeon/llvm: Remove AMDIL GLOBALSTORE* instructionsTom Stellard2012-06-014-77/+36
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* radeon/llvm: Remove AMDIL GLOBALLOAD* instructionsTom Stellard2012-06-016-128/+24
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* radeon/llvm: Update and fix some commentsTom Stellard2012-05-292-12/+6
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* radeonsi: Remove use.sgpr* intrinsics, use load instructions insteadTom Stellard2012-05-294-30/+21
| | | | | | | | | | We now model loading uses sgpr values with LLVM IR load instructions that use the USER_SGPR address space. The definition of the sgpr parameter to the use_sgpr() helper function in radeonsi_shader.c has changed so that you can pass raw sgpr values rather than having to divide the sgpr value you want to use by the dword width of the type you want to load.
* radeonsi: Handle TGSI CONST registersTom Stellard2012-05-2911-58/+171
| | | | | We now emit LLVM load instructions for TGSI CONST register reads, which are lowered in the backend to S_LOAD_DWORD* instructions.
* radeon/llvm: Remove AMDILIntrinsicInfo::GetDeclaration fuction bodyTom Stellard2012-05-291-20/+1
| | | | | | | This function was causing compile errors in the tablegen'd code for some intrinsic definitions. I don't think we really need this function, so I'm removing the function body just as a temporary solution. I'll look into removing the entire AMDILIntrinsicInfo class later.
* radeon/llvm: Remove AMDILTargetMachineTom Stellard2012-05-2919-363/+90
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* radeon/llvm: Use a custom inserter for MASK_WRITETom Stellard2012-05-254-34/+36
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