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path: root/src/gallium/drivers/radeon/r600_pipe_common.h
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* radeonsi: remove DBG_PRECOMPILEMarek Olšák2018-01-311-1/+0
| | | | | | it's useless and shader-db stats only report the main shader part. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: use a separate allocator for fine fencesMarek Olšák2017-12-061-0/+1
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: make shader binaries use read-only memoryMarek Olšák2017-12-061-0/+1
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove r600_common_screenMarek Olšák2017-11-291-87/+15
| | | | | | | | | | Most files in gallium/radeon now include si_pipe.h. chip_class and family are now here: sscreen->info.family sscreen->info.chip_class Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove r600_pipe_common::barrier_flags::compute_to_L2Marek Olšák2017-11-291-5/+0
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove query/apply_opaque_metadata callbacksMarek Olšák2017-11-291-8/+0
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move shader debug helpers out of r600_pipe_common.cMarek Olšák2017-11-291-4/+0
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: dismantle si_common_screen_init/destroyMarek Olšák2017-11-291-3/+0
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: set all pipe buffer functions in r600_buffer_common.cMarek Olšák2017-11-291-15/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove more functions from r600_pipe_common.cMarek Olšák2017-11-291-2/+0
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move/remove ac_shader_binary helpersMarek Olšák2017-11-291-3/+0
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove R600_CONTEXT_* flagsMarek Olšák2017-11-291-7/+0
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove some definitions and helpers from r600_pipe_common.hMarek Olšák2017-11-291-102/+0
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove r600_common_context::clear_bufferMarek Olšák2017-11-291-4/+0
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move r600_test_dma.c into si_test_dma.cMarek Olšák2017-11-291-3/+0
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move all clear() code into si_clear.cMarek Olšák2017-11-291-8/+5
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: enable DCC with MSAA for VIMarek Olšák2017-11-291-0/+3
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove has_cp_dma, has_streamout flags (v2)Marek Olšák2017-11-141-2/+0
| | | | v2: remove r600_can_dma_copy_buffer
* radeonsi: pack r600_surface betterMarek Olšák2017-11-091-11/+11
| | | | | | 160 -> 136 bytes Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: pack r600_texture betterMarek Olšák2017-11-091-27/+26
| | | | | | 1752 -> 1736 bytes Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: clean up r600_surfaceMarek Olšák2017-11-091-26/+11
| | | | | | 216 -> 160 bytes Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove r600_texture::non_disp_tilingMarek Olšák2017-11-091-2/+0
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove DBG_NO_DISCARD_RANGEMarek Olšák2017-11-091-1/+0
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move pipe debug callback to si_contextNicolai Hähnle2017-11-091-1/+0
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: use ac_get_llvm_processor_nameMarek Olšák2017-11-071-1/+0
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: don't map big VRAM buffers for the first upload directlyMarek Olšák2017-11-061-0/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: Add R600_DEBUG flag to reserve VMID per ctx.Andrey Grodzovsky2017-11-031-0/+1
| | | | | | | | | | Fixes reverted patch f03b7c9 by doing VMID reservation per process and not per context. Also updates required amdgpu libdrm version since the change involved interface updates in amdgpu libdrm. Signed-off-by: Andrey Grodzovsky <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeonsi: remove 'Authors:' commentsMarek Olšák2017-11-021-3/+0
| | | | | | | It's inaccurate. Instead, see the copyright and use "git log" and "git blame" to know the authorship. Acked-by: Nicolai Hähnle <[email protected]>
* Revert "winsys/amdgpu: Add R600_DEBUG flag to reserve VMID per ctx."Marek Olšák2017-11-011-1/+0
| | | | | | This reverts commit f03b7c9ad92c1656a221297819fbc6d065cc0af7. The libdrm interface is wrong.
* winsys/amdgpu: Add R600_DEBUG flag to reserve VMID per ctx.Andrey Grodzovsky2017-10-311-0/+1
| | | | | Signed-off-by: Andrey Grodzovsky <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeonsi: import cayman_msaa.c from drivers/radeonMarek Olšák2017-10-091-25/+0
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: import r600_streamout from drivers/radeonMarek Olšák2017-10-091-57/+0
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: disable primitive binning on Vega10 (v2)Marek Olšák2017-10-091-0/+2
| | | | | | | | | | | | | | | Our driver implementation is known to decrease performance for some tests, but we don't know if any apps and benchmarks (e.g. those tested by Phoronix) are affected. This disables the feature just to be safe. Set this to enable partial primitive binning: R600_DEBUG=dpbb Set this to enable full primitive binning: R600_DEBUG=dpbb,dfsm v2: add new debug options Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: enumerize DBG flagsMarek Olšák2017-10-091-49/+61
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move si_draw_rectangle into si_state_draw.cMarek Olšák2017-10-071-5/+0
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: remove r600_atom::num_dwMarek Olšák2017-10-071-2/+0
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: remove old r600g code checking chip_class and familyMarek Olšák2017-10-071-20/+0
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move current_rast_prim into si_contextNicolai Hähnle2017-10-021-1/+0
| | | | | | v2: rebase fixes Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: move and rename scissor and viewport state and functionsNicolai Hähnle2017-10-021-35/+0
| | | | | | v2: change GET_MAX_SCISSOR to SI_MAX_SCISSOR Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: remove si_apply_scissor_bug_workaroundNicolai Hähnle2017-10-021-2/+0
| | | | | | It only affects pre-SI chips. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: move current_rast_prim to r600_common_contextNicolai Hähnle2017-10-021-0/+1
| | | | | | | | | | We'll use it in the scissors / clip / guardband state. v2: avoid a performance regression on r600 when applied to (pre-fork) stable branches Cc: [email protected] Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: clamp depth comparison value only for fixed point formatsNicolai Hähnle2017-09-291-0/+1
| | | | | | | | | | | | | | | | | | | The hardware usually does this automatically. However, we upgrade depth to Z32_FLOAT to enable TC-compatible HTILE, which means the hardware no longer clamps the comparison value for us. The only way to tell in the shader whether a clamp is required seems to be to communicate an additional bit in the descriptor table. While VI has some unused bits in the resource descriptor, those bits have unfortunately all been used in gfx9. So we use an unused bit in the sampler state instead. Fixes dEQP-GLES3.functional.texture.shadow.2d.linear.equal_depth_component32f and many other tests in dEQP-GLES3.functional.texture.shadow.* Fixes: d4d9ec55c589 ("radeonsi: implement TC-compatible HTILE") Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* r600: fork and import gallium/radeonMarek Olšák2017-09-261-144/+135
| | | | | | | | | | | This marks the end of code sharing between r600 and radeonsi. It's getting difficult to work on radeonsi without breaking r600. A lot of functions had to be renamed to prevent linker conflicts. There are also minor cleanups. Acked-by: Dave Airlie <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: enable out-of-order rasterization when possible on VI and GFX9 dGPUsNicolai Hähnle2017-09-181-1/+1
| | | | | | | | | This does not take commutative blending into account yet. R600_DEBUG=nooutoforder disables it. Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* gallium/radeon: pass old_(perfect_)enable to set_occlusion_query_stateNicolai Hähnle2017-09-181-1/+3
| | | | | | | The callee can derive the current enable state itself. Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* gallium/u_blitter: use draw_rectangle callback for layered clearsMarek Olšák2017-09-111-1/+2
| | | | | | | They are done with instancing. Reviewed-by: Nicolai Hähnle <[email protected]> Tested-by: Brian Paul <[email protected]>
* gallium/u_blitter: add new union blitter_attrib to replace pipe_color_unionMarek Olšák2017-09-111-1/+1
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Tested-by: Brian Paul <[email protected]>
* radeonsi/gfx9: implement primitive binningMarek Olšák2017-09-051-0/+2
| | | | | | | This increases performance, but it was tuned for Raven, not Vega. We don't know yet how Vega will perform, hopefully not worse. Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: sort DBG shader flags according to pipe_shader_typeMarek Olšák2017-09-041-13/+12
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: ensure cache flushes happen before SET_PREDICATION packetsNicolai Hähnle2017-09-041-1/+2
| | | | | | | | The data is read when the render_cond_atom is emitted, so we must delay emitting the atom until after the flush. Fixes: 0fe0320dc074 ("radeonsi: use optimal packet order when doing a pipeline sync") Reviewed-by: Marek Olšák <[email protected]>
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