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	Commit message (Expand)	Author	Age	Files	Lines
*	radeon/llvm: Match integer add/sub for SI.	Michel Dänzer	2012-09-17	1	-2/+8
*	radeon/llvm: Complete integer comparison patterns for SI.	Michel Dänzer	2012-09-17	1	-4/+12
*	radeon/llvm: Match AMDGPUfract on SI.	Michel Dänzer	2012-09-17	1	-1/+3
*	radeon/llvm: Match int_AMDGPU_floor for SI.	Michel Dänzer	2012-09-17	1	-1/+3
*	radeon/llvm: Match vector logical operations on SI.	Michel Dänzer	2012-09-17	1	-3/+9
*	radeon/llvm: Support frint on SI	Christian König	2012-09-14	1	-1/+3
*	radeon/llvm: Fix lowering of vbuild	Tom Stellard	2012-09-13	1	-2/+2
*	radeon/llvm: Support fmul on SI	Tom Stellard	2012-09-13	1	-1/+4
*	radeonsi: Handle position input parameter for pixel shaders v2	Tom Stellard	2012-09-11	1	-0/+20
*	radeon/llvm: Match fexp2 for SI.	Michel Dänzer	2012-09-07	1	-1/+3
*	radeon/llvm: Add intrinsic for enabling whole quad mode in SI pixel shaders.	Michel Dänzer	2012-09-06	1	-0/+7
*	radeon/llvm: Fix operand ordering for V_CNDMASK_B32	Tom Stellard	2012-09-05	1	-3/+3
*	radeon/llvm: Use correct float->int conversion opcode on SI.	Tom Stellard	2012-09-05	1	-2/+4
*	radeon/llvm: Fix encoding of V_CNDMASK_B32	Tom Stellard	2012-09-04	1	-2/+2
*	radeon/llvm: Rework how immediate operands are handled with SI	Tom Stellard	2012-08-31	1	-8/+19
*	radeon/llvm: Add support for RCP instruction on SI	Tom Stellard	2012-08-31	1	-1/+3
*	radeon/llvm: Support AMDGPUfmin DAG node on SI	Tom Stellard	2012-08-31	1	-1/+3
*	radeon/llvm: Create a register class for the M0 register	Tom Stellard	2012-08-29	1	-7/+8
*	radeon/llvm: Set the neverHasSideEffects bit on more instructions	Tom Stellard	2012-08-29	1	-0/+2
*	radeon/llvm: Handle TGSI KIL opcode for SI.	Michel Dänzer	2012-08-28	1	-0/+7
*	radeon/llvm: Basic support for SI EXEC register.	Michel Dänzer	2012-08-28	1	-2/+13
*	radeonsi: Use FP16 shader export format when necessary / possible.	Michel Dänzer	2012-08-27	1	-1/+3
*	radeon/llvm: Lower RETFLAG DAG Node to S_ENDPGM on SI	Tom Stellard	2012-08-23	1	-1/+4
*	radeon/llvm: Lower loads from USE_SGPR adddress space during DAG lowering	Tom Stellard	2012-08-15	1	-27/+0
*	radeon/llvm: Add live-in registers during DAG lowering	Tom Stellard	2012-08-15	1	-16/+0
*	radeon/llvm: Add support for more f32 CMP instructions on SI	Tom Stellard	2012-08-02	1	-5/+15
*	radeon/llvm: Add support for fneg on SI	Tom Stellard	2012-08-02	1	-0/+1
*	radeon/llvm: Add support for fp_to_sint on SI	Tom Stellard	2012-08-02	1	-1/+3
*	radeonsi: Handle TGSI DIV opcode.	Michel Dänzer	2012-08-02	1	-0/+5
*	radeon/llvm: Add pseudo-support for 64-bit immediate types on SI	Tom Stellard	2012-07-31	1	-0/+12
*	radeon/llvm: Rename all AMDIL* classes to AMDGPU*	Tom Stellard	2012-07-30	1	-2/+2
*	radeon/llvm: Add instruction defs for branches on SI	Tom Stellard	2012-07-27	1	-15/+113
*	radeon/llvm: Fix VOPC and V_CNDMASK encoding	Tom Stellard	2012-07-27	1	-4/+6
*	radeon/llvm: Add special nodes for SALU operations on VCC	Tom Stellard	2012-07-27	1	-1/+17
*	radeon/llvm: Add bitconvert patterns for SI	Tom Stellard	2012-07-27	1	-0/+6
*	radeon/llvm: Use multiclasses for floating point loads	Tom Stellard	2012-07-11	1	-1/+2
*	radeonsi: Handle SUB_f32.	Thomas Stellard	2012-06-12	1	-1/+3
*	radeon/llvm: Remove AMDIL VCREATE* instructions	Tom Stellard	2012-06-06	1	-0/+3
*	radeon/llvm: Remove AMDIL LOADCONST* instructions	Tom Stellard	2012-06-06	1	-7/+10
*	radeonsi: Remove use.sgpr* intrinsics, use load instructions instead	Tom Stellard	2012-05-29	1	-24/+16
*	radeonsi: Handle TGSI CONST registers	Tom Stellard	2012-05-29	1	-28/+18
*	radeon/llvm: Use a custom inserter to lower CLAMP	Tom Stellard	2012-05-25	1	-0/+1
*	radeon/llvm: Use a custom inserter to lower FABS	Tom Stellard	2012-05-25	1	-0/+1
*	radeon/llvm: Remove auto-generated AMDIL->ISA conversion code	Tom Stellard	2012-05-24	1	-4/+1
*	radeon/llvm: Remove AMDIL MAD instruction defs	Tom Stellard	2012-05-17	1	-0/+8
*	radeon/llvm: Remove AMDIL floating-point ADD instruction defs	Tom Stellard	2012-05-17	1	-1/+4
*	radeon/llvm: Add custom SDNodes for MAX	Tom Stellard	2012-05-17	1	-2/+3
*	radeonsi: Flesh out shader interpolation related code.	Michel Dänzer	2012-05-14	1	-0/+18
*	radeon/llvm: Add some comments	Tom Stellard	2012-05-10	1	-5/+1
*	radeon/llvm: Make sure the LOAD_CONST def uses the isSI predicate	Tom Stellard	2012-05-09	1	-0/+7