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	Commit message (Expand)	Author	Age	Files	Lines
*	radeon/llvm: Add instruction defs for branches on SI	Tom Stellard	2012-07-27	1	-15/+113
*	radeon/llvm: Fix VOPC and V_CNDMASK encoding	Tom Stellard	2012-07-27	1	-4/+6
*	radeon/llvm: Add special nodes for SALU operations on VCC	Tom Stellard	2012-07-27	1	-1/+17
*	radeon/llvm: Add bitconvert patterns for SI	Tom Stellard	2012-07-27	1	-0/+6
*	radeon/llvm: Use multiclasses for floating point loads	Tom Stellard	2012-07-11	1	-1/+2
*	radeonsi: Handle SUB_f32.	Thomas Stellard	2012-06-12	1	-1/+3
*	radeon/llvm: Remove AMDIL VCREATE* instructions	Tom Stellard	2012-06-06	1	-0/+3
*	radeon/llvm: Remove AMDIL LOADCONST* instructions	Tom Stellard	2012-06-06	1	-7/+10
*	radeonsi: Remove use.sgpr* intrinsics, use load instructions instead	Tom Stellard	2012-05-29	1	-24/+16
*	radeonsi: Handle TGSI CONST registers	Tom Stellard	2012-05-29	1	-28/+18
*	radeon/llvm: Use a custom inserter to lower CLAMP	Tom Stellard	2012-05-25	1	-0/+1
*	radeon/llvm: Use a custom inserter to lower FABS	Tom Stellard	2012-05-25	1	-0/+1
*	radeon/llvm: Remove auto-generated AMDIL->ISA conversion code	Tom Stellard	2012-05-24	1	-4/+1
*	radeon/llvm: Remove AMDIL MAD instruction defs	Tom Stellard	2012-05-17	1	-0/+8
*	radeon/llvm: Remove AMDIL floating-point ADD instruction defs	Tom Stellard	2012-05-17	1	-1/+4
*	radeon/llvm: Add custom SDNodes for MAX	Tom Stellard	2012-05-17	1	-2/+3
*	radeonsi: Flesh out shader interpolation related code.	Michel Dänzer	2012-05-14	1	-0/+18
*	radeon/llvm: Add some comments	Tom Stellard	2012-05-10	1	-5/+1
*	radeon/llvm: Make sure the LOAD_CONST def uses the isSI predicate	Tom Stellard	2012-05-09	1	-0/+7
*	radeon/llvm: Remove the ReorderPreloadInstructions pass	Tom Stellard	2012-05-08	1	-3/+0
*	r600g/llvm: Let ISel handle lowering to {INSERT,EXTRACT}_SUBREG	Tom Stellard	2012-04-23	1	-17/+0
*	radeonsi: initial WIP SI code	Tom Stellard	2012-04-13	1	-0/+962