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path: root/src/gallium/drivers/radeon/SIInstructions.td
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* radeon/llvm: Match integer add/sub for SI.Michel Dänzer2012-09-171-2/+8
* radeon/llvm: Complete integer comparison patterns for SI.Michel Dänzer2012-09-171-4/+12
* radeon/llvm: Match AMDGPUfract on SI.Michel Dänzer2012-09-171-1/+3
* radeon/llvm: Match int_AMDGPU_floor for SI.Michel Dänzer2012-09-171-1/+3
* radeon/llvm: Match vector logical operations on SI.Michel Dänzer2012-09-171-3/+9
* radeon/llvm: Support frint on SIChristian König2012-09-141-1/+3
* radeon/llvm: Fix lowering of vbuildTom Stellard2012-09-131-2/+2
* radeon/llvm: Support fmul on SITom Stellard2012-09-131-1/+4
* radeonsi: Handle position input parameter for pixel shaders v2Tom Stellard2012-09-111-0/+20
* radeon/llvm: Match fexp2 for SI.Michel Dänzer2012-09-071-1/+3
* radeon/llvm: Add intrinsic for enabling whole quad mode in SI pixel shaders.Michel Dänzer2012-09-061-0/+7
* radeon/llvm: Fix operand ordering for V_CNDMASK_B32Tom Stellard2012-09-051-3/+3
* radeon/llvm: Use correct float->int conversion opcode on SI.Tom Stellard2012-09-051-2/+4
* radeon/llvm: Fix encoding of V_CNDMASK_B32Tom Stellard2012-09-041-2/+2
* radeon/llvm: Rework how immediate operands are handled with SITom Stellard2012-08-311-8/+19
* radeon/llvm: Add support for RCP instruction on SITom Stellard2012-08-311-1/+3
* radeon/llvm: Support AMDGPUfmin DAG node on SITom Stellard2012-08-311-1/+3
* radeon/llvm: Create a register class for the M0 registerTom Stellard2012-08-291-7/+8
* radeon/llvm: Set the neverHasSideEffects bit on more instructionsTom Stellard2012-08-291-0/+2
* radeon/llvm: Handle TGSI KIL opcode for SI.Michel Dänzer2012-08-281-0/+7
* radeon/llvm: Basic support for SI EXEC register.Michel Dänzer2012-08-281-2/+13
* radeonsi: Use FP16 shader export format when necessary / possible.Michel Dänzer2012-08-271-1/+3
* radeon/llvm: Lower RETFLAG DAG Node to S_ENDPGM on SITom Stellard2012-08-231-1/+4
* radeon/llvm: Lower loads from USE_SGPR adddress space during DAG loweringTom Stellard2012-08-151-27/+0
* radeon/llvm: Add live-in registers during DAG loweringTom Stellard2012-08-151-16/+0
* radeon/llvm: Add support for more f32 CMP instructions on SITom Stellard2012-08-021-5/+15
* radeon/llvm: Add support for fneg on SITom Stellard2012-08-021-0/+1
* radeon/llvm: Add support for fp_to_sint on SITom Stellard2012-08-021-1/+3
* radeonsi: Handle TGSI DIV opcode.Michel Dänzer2012-08-021-0/+5
* radeon/llvm: Add pseudo-support for 64-bit immediate types on SITom Stellard2012-07-311-0/+12
* radeon/llvm: Rename all AMDIL* classes to AMDGPU*Tom Stellard2012-07-301-2/+2
* radeon/llvm: Add instruction defs for branches on SITom Stellard2012-07-271-15/+113
* radeon/llvm: Fix VOPC and V_CNDMASK encodingTom Stellard2012-07-271-4/+6
* radeon/llvm: Add special nodes for SALU operations on VCCTom Stellard2012-07-271-1/+17
* radeon/llvm: Add bitconvert patterns for SITom Stellard2012-07-271-0/+6
* radeon/llvm: Use multiclasses for floating point loadsTom Stellard2012-07-111-1/+2
* radeonsi: Handle SUB_f32.Thomas Stellard2012-06-121-1/+3
* radeon/llvm: Remove AMDIL VCREATE* instructionsTom Stellard2012-06-061-0/+3
* radeon/llvm: Remove AMDIL LOADCONST* instructionsTom Stellard2012-06-061-7/+10
* radeonsi: Remove use.sgpr* intrinsics, use load instructions insteadTom Stellard2012-05-291-24/+16
* radeonsi: Handle TGSI CONST registersTom Stellard2012-05-291-28/+18
* radeon/llvm: Use a custom inserter to lower CLAMPTom Stellard2012-05-251-0/+1
* radeon/llvm: Use a custom inserter to lower FABSTom Stellard2012-05-251-0/+1
* radeon/llvm: Remove auto-generated AMDIL->ISA conversion codeTom Stellard2012-05-241-4/+1
* radeon/llvm: Remove AMDIL MAD instruction defsTom Stellard2012-05-171-0/+8
* radeon/llvm: Remove AMDIL floating-point ADD instruction defsTom Stellard2012-05-171-1/+4
* radeon/llvm: Add custom SDNodes for MAXTom Stellard2012-05-171-2/+3
* radeonsi: Flesh out shader interpolation related code.Michel Dänzer2012-05-141-0/+18
* radeon/llvm: Add some commentsTom Stellard2012-05-101-5/+1
* radeon/llvm: Make sure the LOAD_CONST def uses the isSI predicateTom Stellard2012-05-091-0/+7
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