Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | radeon/llvm: Move SMRD IMM pattern before SMRD SGPR pattern | Tom Stellard | 2012-07-31 | 1 | -7/+6 |
* | radeon/llvm: Add instruction defs for branches on SI | Tom Stellard | 2012-07-27 | 1 | -2/+9 |
* | radeon/llvm: Fix VOPC and V_CNDMASK encoding | Tom Stellard | 2012-07-27 | 1 | -4/+3 |
* | radeon/llvm: Add special nodes for SALU operations on VCC | Tom Stellard | 2012-07-27 | 1 | -0/+19 |
* | radeon/llvm: Use multiclasses for floating point loads | Tom Stellard | 2012-07-11 | 1 | -0/+5 |
* | radeon/llvm: Don't set the IMM bit in SMRD instruction definitions. | Tom Stellard | 2012-07-11 | 1 | -7/+2 |
* | radeonsi: Handle TGSI CONST registers | Tom Stellard | 2012-05-29 | 1 | -24/+38 |
* | radeon/llvm: Add some comments | Tom Stellard | 2012-05-10 | 1 | -5/+1 |
* | radeon/llvm: Make sure the LOAD_CONST def uses the isSI predicate | Tom Stellard | 2012-05-09 | 1 | -7/+0 |
* | radeonsi: MIMG shader instructions require waiting for the results. | Michel Dänzer | 2012-04-19 | 1 | -0/+2 |
* | radeonsi: initial WIP SI code | Tom Stellard | 2012-04-13 | 1 | -0/+472 |