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	Commit message (Expand)	Author	Age	Files	Lines
*	radeon/llvm: Add intrinsic for enabling whole quad mode in SI pixel shaders.	Michel Dänzer	2012-09-06	1	-0/+2
*	radeon/llvm: Rework how immediate operands are handled with SI	Tom Stellard	2012-08-31	1	-0/+2
*	radeon/llvm: Create a register class for the M0 register	Tom Stellard	2012-08-29	1	-1/+1
*	radeon/llvm: Handle TGSI KIL opcode for SI.	Michel Dänzer	2012-08-28	1	-0/+2
*	radeon/llvm: Lower loads from USE_SGPR adddress space during DAG lowering	Tom Stellard	2012-08-15	1	-2/+1
*	radeon/llvm: Add SI DAG optimizations for setcc, select_cc	Tom Stellard	2012-07-27	1	-0/+1
*	radeon/llvm: Add special nodes for SALU operations on VCC	Tom Stellard	2012-07-27	1	-0/+3
*	radeon/llvm: Add custom lowering for SELECT_CC nodes on SI	Tom Stellard	2012-07-27	1	-0/+1
*	radeon/llvm: Implement getSetCCResultType for SI	Tom Stellard	2012-07-27	1	-0/+1
*	radeon/llvm: Custom lower BR_CC for SI	Tom Stellard	2012-07-27	1	-0/+4
*	radeon/llvm: More comments and cleanups	Tom Stellard	2012-05-11	1	-0/+4
*	radeon/llvm: Add some comments	Tom Stellard	2012-05-10	1	-2/+2
*	radeonsi: initial WIP SI code	Tom Stellard	2012-04-13	1	-0/+44